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Freescale Semiconductor

Application Note

Document Number: AN4034

Rev. 0, 03/2011

Contents

© Freescale Semiconductor, Inc., 2011. All rights reserved.

1

Scope

This paper is a brief tutorial and description on how to 
select and run the MPC5643L in decoupled parallel 
mode (DPM).

2

Reference material

Freescale document MPC5643LRM, 

MPC5643L 

Microcontroller Reference Manual

, Rev. 7, October 

2010.

3

Overview

The paper reviews the dual core modes of the 
MPC5643L, but focuses on the operation of the 
decoupled parallel mode (DP mode or DPM) on the chip 
and on how to enable the DPM.

The MPC5643L operates in both lock step mode and 
DPM — this paper will focus on the DPM mode.

1

Scope  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2

Reference material  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

4

MPC5643L dual core architecture . . . . . . . . . . . . . . . . . . 2

4.1

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

4.2

Sphere of replication . . . . . . . . . . . . . . . . . . . . . . . . 3

4.3

Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5

Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5.1

Hardware setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5.2

Software setup  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5.3

Basic dual core flash boot program flow . . . . . . . . . 5

6

Changing between LSM and DPM  . . . . . . . . . . . . . . . . . 7

6.1

Configure the flash programming utility . . . . . . . . . . 7

6.2

Dump shadow flash to s-record file . . . . . . . . . . . . . 8

6.3

Modify s-record file to change LSM/DPM configuration
8

6.4

Program shadow flash with updated user configura-
tion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

6.5

Verify new configuration  . . . . . . . . . . . . . . . . . . . . . 9

7

Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

8

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Qorivva MPC5643L Dual 
Processor Mode

by: Mark Ruthenbeck

Applications Engineering
Microcontroller Solutions Group

Summary of Contents for Qorivva MPC5643L

Page 1: ...The MPC5643L operates in both lock step mode and DPM this paper will focus on the DPM mode 1 Scope 1 2 Reference material 1 3 Overview 1 4 MPC5643L dual core architecture 2 4 1 Block diagram 3 4 2 Sp...

Page 2: ...on as about 1 6 the performance of the LS mode at the same frequency In the DP mode each CPU core and each connected channel run independently from the other one and redundancy checkers RCCU are disab...

Page 3: ...ual processor mode these same peripherals have unique addresses On core 0 the SoR peripherals remain at the LSM addresses and the core 1 SoR peripherals are now visible at a different set of addresses...

Page 4: ...r configuration is located at offset 0x3E10 This is also readable at flash register BIU4 Flash_regs_base 0x2C Refer to Section 6 Changing between LSM and DPM for detailed instructions on how to progra...

Page 5: ...flow For dual core booting the key concept to understand is that dual core boot is nothing more than a typical single core boot except that it starts another single core boot The initialization of in...

Page 6: ...0 setting up the start address for core 1 Place Reset Vector for Core 1 in register P2BOOT Release Reset for Core 1 by writing DPMKEY No Core 1 runs MMU setup other initialization including NMI vector...

Page 7: ...pon return from the NMI both cores are now fully functional and operating independently It is important for the NMI routines to be included because the NMI interrupt is triggered when the system moves...

Page 8: ...configuration 1 From the menu bar select Upload Upload Module 2 Specify a name for the s record s19 file 6 3 Modify s record file to change LSM DPM configuration The s record file can now be edited to...

Page 9: ...This change requires the checksum to be recalculated as follows 0xFF 0x14 0xFF 0xFE 0x10 0xFF 0xBF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF mod 256 0x2E Example 2 Modifie...

Page 10: ...cond core requires the same kind of initialization code as used on the first core So the end result is really a single core with peripherals times two There is no additional complexity of code only ad...

Page 11: ...validated for each customer application by customer s technical experts Freescale does not convey any license under its patent rights nor the rights of others Freescale sells products pursuant to stan...

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