2.19 MCU Port AD Header, J41
The MCU signals from GPIO port AD can be monitored using this header.
Table 17. MCU Port AD header
Interface pin
MCU signal
Pin functionality
1
PAD0
PAD0/KWAD0/AMP0/AN0_0
2
PAD1
PAD1/KWAD1/AMPM0/AN0_1
3
PAD2
PAD2/KWAD2/AMPP0/AN0_2
4
PAD3
PAD3/KWAD3/AN0_3/
5
PAD4
PAD4/KWAD4/AN0_4/
6
PAD5
PAD5/KWAD5/AMP1/AN1_0
7
PAD6
PAD6/KWAD6/AMPM1/AN1_1/(SS)
8
PAD7
PAD7/KWAD7/AMPP1/AN1_2
9
PAD8
PAD8/KWAD8/AN1_3/VRH
10
GND
Ground reference
3 Design Considerations
This section provides additional information about the functional blocks of the S12ZVMx12EVB motor control board.
3.1 MC9S12ZVM Features
The MC9S12ZVM-Family is an automotive 16-bit microcontroller family using the 180 nm NVM + UHV technology that
offers the capability to integrate 40 V analog components. The particular differentiating features of this family are the
enhanced S12Z core, the combination of dual-ADC synchronized with PWM generation and the integration of “high-voltage”
analog modules, including the voltage regulator (VREG), Gate Driver Unit (GDU) and a Local Interconnect Network (LIN)
physical layer. These features enable a fully integrated single chip solution to drive up to 6 external power MOSFETs for
BLDC or PMSM motor drive applications.
• S12Z CPU core
• Memory
• 128, 64 or 32 KB on-chip flash with ECC
• 512 byte EEPROM with ECC
• 8, 4, or 2 KB on-chip SRAM with ECC
• Clock Modules
• Phase locked loop (IPLL) frequency multiplier with internal filter
• 1 MHz internal RC oscillator with +/-1.3% accuracy over rated temperature range
• 4-16 MHz amplitude controlled pierce oscillator
• Internal COP (watchdog) module
• Autonomous periodic interrupt (API)
• Low side and high side FET pre-drivers for each phase
• Gate drive pre-regulator
• LDO (Low Dropout Voltage Regulator) (typically 11 V)
• High side gate supply generated using bootstrap circuit with external diode and capacitor
Design Considerations
S12ZVM12EVB Evaluation Board User Guide, Rev. 2, 03/2016
Freescale Semiconductor, Inc.
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