NXP Semiconductors S32G2 Configuration Manual Download

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DFS

S32G2 Vehicle Network Processor - Clock Configuration Guide, Rev. 1, 11/2021

NXP Semiconductors

Figure 2. DFS block diagram

The user needs to configure the value for the below parameters to achieve the target frequencies for
CORE_DFSn and PERIPH_DFSn.

PLL_VCO : Respective PLL_VCO frequency serves an input clock source to the DFS block.

MFI : Integer part of LDF.

MFN : Numerator of fractional LDF

Summary of Contents for S32G2

Page 1: ...esizer DFS modules This application note is intended to provide the user values for commonly used PLL DFS configurations This document is accompanied with an attached clock configurator S32G2_Clock_Co...

Page 2: ...further diving into this document The following table shows the abbreviations used throughout the document Table1 Acronyms and abbreviations Abbreviation Explanation DFS Digital Frequency Synthesizer...

Page 3: ...Ls can either be the 20 40 MHz FXOSC or 48 MHz FIRC During boot FIRC_CLK is used as the default PLL reference clock After boot the PLL reference must be changed to FXOSC_CLK Ensure that PLLCLKMUX REFC...

Page 4: ...ter jitter performance 2 MFI Integer part of LDF 3 MFN Numerator of fractional LDF 4 DIV Division value 5 STEPSIZE Step size for modulation depth and frequency in frequency modulation mode 6 STEPNO Nu...

Page 5: ...igure 2 DFS block diagram The user needs to configure the value for the below parameters to achieve the target frequencies for CORE_DFSn and PERIPH_DFSn 1 PLL_VCO Respective PLL_VCO frequency serves a...

Page 6: ...ns tab The options tab provides an interface to select the following 1 FXOSC frequency Figure 3 Selecting FXOSC frequency 2 RDIV RDIV is selected individually for each PLL CORE_PLL PERIPH_PLL ACCEL_PL...

Page 7: ...n example for A53_CORE_CLK In case SSCG is disabled the calculator provides 500 MHz 800 MHz and 1000 MHz frequency options Figure 8 FA53_CORE_CLK with SSCG disabled And when SSCG modulation is enabled...

Page 8: ...selected parameters 4 3 Spread spectrum tab With the help of this tab user can calculate values for STEPNO and STEPSIZE to program the modulation depth and the modulation frequency The calculator take...

Page 9: ...me precaution needs to be taken care while updating the FXOSC frequency in Spread Spectrum tab 2 Target frequency As explained above caution needs to be exercised while enabling or disabling the SSCG...

Page 10: ...regulated EMI requirements This section provides the user instructions on how to enable Spread Spectrum functionality For S32G2 Spread Spectrum clock modulation is only available for the Core Acceler...

Page 11: ...modulation depth may differ from the intended modulation depth because of rounding operations applied to PLLFM STEPSIZE and PLLFM STEPNO 5 2 Spread Spectrum Considerations User must adhere to the belo...

Page 12: ...ere to below conditions 1 18432 2 REF 100 PLL_VCO 5 3 Example code This section illustrates how to configure modulation frequency and modulation depth with the help of an example Example Enabling SSCG...

Page 13: ...LLDV B MFI 49 CORE_PLL PLLFD B MFN 11520 Enable SSCG at 64 KHz CORE_PLL PLLFM B SSCGBYP 0 Spread spectrum modulation is not bypassed CORE_PLL PLLFM B SPREADCTL 0 Center Spread modulation fMOD 64 KHz M...

Page 14: ...Clock Configuration using S32DS Clocks Tool S32G2 Vehicle Network Processor Clock Configuration Guide Rev 1 11 2021 14 NXP Semiconductors Figure 17 Clocks diagram view...

Page 15: ...ration Guide Rev 1 11 2021 NXP Semiconductors 15 Figure 18 Clock Register view NOTE Similar clock configuration can also be done using EB tresos 7 References 1 S32G2 Reference Manual 2 S32G2 Data Shee...

Page 16: ...the effect of these vulnerabilities on customer s applications and products and NXP accepts no liability for any vulnerability that is discovered Customers should implement appropriate design and ope...