Clock calculator design
S32G2 Vehicle Network Processor - Clock Configuration Guide, Rev. 1, 11/2021
NXP Semiconductors
7
5.
Target Frequency – Select the target frequency.
Figure 7. Selecting the clock frequency
In case of CORE_PLL, DDR_PLL, ACCEL_PLL, the sheet lists a set of frequencies to support
the SSCG disabled case and the corresponding set of frequencies with 1.5% modulation depth
for SSCG enabled case.
As an example for A53_CORE_CLK : In case SSCG is disabled, the calculator provides 500
MHz, 800 MHz and 1000 MHz frequency options.
Figure 8. F
A53_CORE_CLK
with SSCG disabled
And when SSCG modulation is enabled, the calculator provides frequency options with 1.5%
modulation depth - 496.3 MHz, 794 MHz, 992.5 MHz.
Figure 9. F
A53_CORE_CLK
with SSCG enabled
4.2 Configuration tab
After selecting the parameters in the options tab, the calculator provides the value for PLL parameters
(MFI, MFN, DIV), DFS parameters (MFI, MFN) and MC_CGM parameters (SELCTL, DIV) in the
configurations tab on the basis of the selection in the options tab.
