NXP Semiconductors
UM11665
SC18IS604-EVB evaluation board
JP4 – I2C Header
Function
1
SCL
2
GROUND
3
VCC
4
SDA
Table 3. JP4 - I2C header
JP2 – GPIO
Function
1
GPIO0
2
GPIO1
3
GPIO2
4
GPIO3
5
GPIO4
6
GROUND
Table 4. JP2 - GPIO
4.3 Schematic, board layout and bill of materials
The schematic, board layout and bill of materials for the SC18IS604-EVB evaluation
http://www.nxp.com/SC18IS604-EVB
.
4.4 Sample control sequences from SPI master
4.4.1 Register read
0x21 0x00 0xFF // Read register 0x00 where 0xFF is an SPI dummy byte
4.4.2 Register write
0x20 0x00 0xAA // Write register 0x00 with AA
4.4.3 GPIO as input
0x20 0x00 0x00 // program GPIOs as inputs
0x21 0x01 0xFF // read IOState register
4.4.4 GPIO as output
0x20 0x00 0xAA // program GPIOs as output (push-pull)0x21 0x01
0x20 0x01 0xXX // write to IOState register to set GPIO pins
UM11665
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© NXP B.V. 2021. All rights reserved.
User manual
Rev. 1.0 — 19 August 2021
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