TWR-56F8400 User’s Manual
Page 7 of 35
The P3_3V power rail provides power to the majority of the circuits on the board including the
MC56F84789 (including the analog power pins through L500 and L501), inverters at U500 and U502, a
buffer at U505, the on board LEDs at D1-D9, the thermistor divider circuits at RT1-RT4, and the pull-up
resistors at R2, R3, R11, R565, R570, and R562.
2.2.3
P3_3V/5V
The P3_3V/5V power rail is derived from the diode OR (using D500 and D501) of a) the P5V_ELEV
power net from the elevator connection (J500 pins A1 and B1), b) the P5V output of the USB power
switch at U501, or c) the P3_3V power rail from J7. When there is a USB cable connected or when the
tower elevator boards are connected this power rail will be a Schottky diode drop (about 0.3V) below
the 5V power nets. When there is no 5V source this power rail will be a Schottky diode drop below the
P3.3V power rail. This allows the inputs of the ICs powered by this rail to stay in a high impedance state
instead of loading down the inputs through the input protection diodes as would happen if there were
no power supplied to the buffers.
2.2.4
Default Power Configuration
The TWR-56F8400 board default power configuration uses the OSBDM/OSJTAG USB port for all power.
As soon as the OSBDM/OSJTAG firmware has started it negotiates with the Host PC USB port for full
USB power. Once approved it enables the 5V USB power switch (U501) which provides 5V to the
P3_3V/5V power rail and to the 3.3V regulator (U1) through headers J10 and J11. Likewise, the on
board voltage regulator provides 3.3V to the P3_3V power rail through headers J6 and J7. The 3.3V
regulator is able to provide up to 700 mA subject to the power dissipation and temperature limits of
the device.
2.3
MC56F84789 DSC
The primary circuits on the board are related to the MC56F84789 DSC. This part is supplied in a surface
mounted 100pin LQFP package at U2. Although the board was laid out to allow a ZIF socket at U3 in
parallel to the chip at U2 the TWR-56F8400 is only available for purchase with the surface mounted
chip.
2.3.1
Clock Sources for the MC56F84789 DSC
Three options are provided for clocking the MC56F84789 device:
1.
Oscillator internal to the MC56F84789 chip – approximately 8 MHz.
2.
8 MHz crystal
3.
External clock input from Primary Tower Connector or the AUX Connector.
The internal oscillator is used to clock the MC56F84789 immediately following reset. This is the default
operation. In this mode the zero ohm resistors at R4 and R10 allow the GPIOC0 and GPIOC1 pins of the
MC56F84789 to be used as inputs or outputs.
