NXP Semiconductors UM11596, User Manual

Page 1: ...formation Information Content Keywords PTN3944 PCIe linear redriver Abstract UM11596 demonstrates application board capability interfacing an PCIe device with a host computer on a x16 slot The applica...

Page 2: ...er application board user manual Rev Date Description 1 20210714 Initial release Revision history UM11596 All information provided in this document is subject to legal disclaimers NXP B V 2021 All rig...

Page 3: ...ly dependent on proper printed circuit board layout and heat sinking design as well as attention to supply filtering transient suppression and I O signal quality The goods provided may not be complete...

Page 4: ...M connector on the top a PCIe device can be attached On the front side of the AIC there are four PTN3944 that redrive PCIe signals from motherboard side from CPU chipset to the PCIe device On the back...

Page 5: ...3 RX_OUT 8 11 x4 x4 RX_IN 8 11 U7 TX_IN 8 11 x4 x4 TX_OUT 12 15 U4 RX_OUT 12 15 x4 x4 RX_IN 12 15 U11 PCA9540 U10 REG1117 3 3 I2C J5 U8 TX_IN 12 15 J13 J17 U9 TPS62827 5 V 1 8 V J12 J11 5 V 3 3 V 3 3...

Page 6: ...ear equalizer application board user manual Figure 3 PTN3944 PCIe add in card back side UM11596 All information provided in this document is subject to legal disclaimers NXP B V 2021 All rights reserv...

Page 7: ...0N TX_IN1P TX_IN1N TX_IN2P TX_IN2N TX_IN3P TX_IN3N TX_OUT0P TX_OUT0N TX_OUT1P TX_OUT1N TX_OUT2P TX_OUT2N TX_OUT3P TX_OUT3N T1_OUT2P T1_OUT1N T1_OUT1P T1_OUT0N TX_OUT0P OUT3N OUT3P ADDR3 ADDR4 ADDR2 AD...

Page 8: ...IN6N TX_IN7P TX_IN7N TX_OUT4P TX_OUT4N TX_OUT5P TX_OUT5N TX_OUT6P TX_OUT6N TX_OUT7P TX_OUT7N TX_OUT6P TX_OUT5N TX_OUT5P TX_OUT4N TX_OUT4P OUT3N OUT3P ADDR3 ADDR4 ADDR2 ADDR1 FG2 FG1 OUT2N OUT2P OUT1N...

Page 9: ..._IN10N TX_IN11P TX_IN11N TX_OUT8P TX_OUT8N TX_OUT9P TX_OUT9N TX_OUT10P TX_OUT10N TX_OUT11P TX_OUT11N TX_OUT10P TX_OUT9N TX_OUT9P TX_OUT8N TX_OUT8P OUT3N OUT3P ADDR3 ADDR4 ADDR2 ADDR1 FG2 FG1 OUT2N OUT...

Page 10: ...N15P TX_IN15N TX_OUT12P TX_OUT12N TX_OUT13P TX_OUT13N TX_OUT14P TX_OUT14N TX_OUT15P TX_OUT15N TX_OUT14P TX_OUT13N TX_OUT13P TX_OUT12N TX_OUT12P OUT3N OUT3P ADDR3 ADDR4 ADDR2 ADDR1 FG2 FG1 OUT2N OUT2P...

Page 11: ...unique I 2 C address See Table 1 Designator I 2 C Address Corresponding PCIe TX Lanes U1 0x23 CH 0 PCIe TX 0 CH 1 PCIe TX 1 CH 2 PCIe TX 2 CH 3 PCIe TX 3 U2 0x22 CH 0 PCIe TX 4 CH 1 PCIe TX 5 CH 2 PC...

Page 12: ..._IN2N RX_IN3P RX_IN3N RX_OUT0P RX_OUT0N RX_OUT1P RX_OUT1N RX_OUT2P RX_OUT2N RX_OUT3P RX_OUT3N RX_OUT2P RX_OUT1N RX_OUT1P RX_OUT0N RX_OUT0P OUT3N OUT3P ADDR3 ADDR4 ADDR2 ADDR1 FG2 FG1 OUT2N OUT2P OUT1N...

Page 13: ...7P RX_IN7N RX_OUT4P RX_OUT4N RX_OUT5P RX_OUT5N RX_OUT6P RX_OUT6N RX_OUT7P RX_OUT7N RX_OUT6P RX_OUT5N RX_OUT5P RX_OUT4N RX_OUT4P OUT3N OUT3P ADDR3 ADDR4 ADDR2 ADDR1 FG2 FG1 OUT2N OUT2P OUT1N OUT1P OUT0...

Page 14: ..._IN11N RX_OUT8P RX_OUT8N RX_OUT9P RX_OUT9N RX_OUT10P RX_OUT10N RX_OUT11P RX_OUT11N RX_OUT10P RX_OUT9N RX_OUT9P RX_OUT8N RX_OUT8P OUT3N OUT3P ADDR3 ADDR4 ADDR2 ADDR1 FG2 FG1 OUT2N OUT2P OUT1N OUT1P OUT...

Page 15: ...RX_IN15N RX_OUT12P RX_OUT12N RX_OUT13P RX_OUT13N RX_OUT14P RX_OUT14N RX_OUT15P RX_OUT15N RX_OUT14P RX_OUT13N RX_OUT13P RX_OUT12N RX_OUT12P OUT3N OUT3P ADDR3 ADDR4 ADDR2 ADDR1 FG2 FG1 OUT2N OUT2P OUT1N...

Page 16: ...Ie RX 3 U6 0x2A CH 0 PCIe RX 4 CH 1 PCIe RX 5 CH 2 PCIe RX 6 CH 3 PCIe RX 7 U7 0x29 CH 0 PCIe RX 8 CH 1 PCIe RX 9 CH 2 PCIe RX 10 CH 3 PCIe RX 11 U8 0x28 CH 0 PCIe RX 12 CH 1 PCIe RX 13 CH 2 PCIe RX 1...

Page 17: ...10 k R80 10 k R81 10 k R82 10 k R83 10 k Figure 16 Front side K5 control switch schematic Switch Switch Position Description 1 U1 Top Front Test Pin Connect To GND 2 U1 Top Front LCTL1 Peaking Gain S...

Page 18: ...ol Setting 4 U2 Top Front FG2 Flat Gain Control Setting 5 U3 Top Front FG1 Flat Gain Control Setting 6 U3 Top Front FG2 Flat Gain Control Setting 7 U4 Top Front FG1 Flat Gain Control Setting K5 8 U4 T...

Page 19: ...8 10 k R89 10 k R90 10 k R91 10 k Figure 19 Back side K6 control switch schematic Switch Switch Position Description 1 U5 Bottom Back Test Pin Connect To GND 2 U5 Bottom Back LCTL1 Peaking Gain Settin...

Page 20: ...ng Setting 1 U5 Bottom Back FG1 Flat Gain Control Setting 2 U5 Bottom Back FG2 Flat Gain Control Setting 3 U6 Bottom Back FG1 Flat Gain Control Setting 4 U6 Bottom Back FG2 Flat Gain Control Setting 5...

Page 21: ...7 RX_OUT3N 7 RX_OUT4P 7 RX_OUT4N PERp5 PERn5 7 RX_OUT5P 7 RX_OUT5N PERp6 PERn6 7 RX_OUT6P 7 RX_OUT6N PERp7 PERn7 7 RX_OUT7P 7 RX_OUT7N RSVD4 GND20 GND21 GND22 GND23 GND24 GND25 GND26 GND27 GND28 GND29...

Page 22: ...RX_IN5N PERp6 PERn6 7 RX_IN6P 7 RX_IN6N PERp7 PERn7 7 RX_IN7P 7 RX_IN7N RSVD_A50 GND_A54 GND_A55 GND_A58 GND_A59 GND_A62 GND_A63 GND_A66 GND_A67 GND_A70 GND_A71 GND_A74 GND_A75 GND_A78 GND_A82 GND_A7...

Page 23: ...An I 2 C MUX U11 on the board is not populated U11 was used to control the previous generation of the device PTN38006 which supported only four I 2 C addresses Since PTN3944 supports up to 32 I 2 C ad...

Page 24: ...se J16 pin 2 3 C187 10 F 25 V aaa 042318 J16 3 pin jumper 3P3V_I2C 5V U10 REG1117 3 3 GND C188 10 F 25 V 3P3V_I2C GND GND 3P3V_CONN 1 2 3 3P3V_PCIE VOUT TAB 2 4 GND 1 VIN 3 Figure 26 Power schematic 3...

Page 25: ...nnected by a 10 pin ribbon cable First attach a 50 mil to 100 mil adapter to the LPCUSBSIO J303 connector Then connect the ribbon cable between the adapter and the J5 connector of the AIC In order to...

Page 26: ...on the J301 connector Do not attach the cable into the PC until instructed 3 Locate SW302 ISP switch on the Sniffer Based Board and hold it down while plug in the micro USB cable to the PC See Figure...

Page 27: ...elect Delete When prompted to delete the file click Yes as shown to confirm that the file should be deleted as shown Figure 32 Deleting the current firmware bin 10 Locate the updated firmware file wit...

Page 28: ...following files File Description Columbus exe GUI executable Click this file to run the GUI liblpcusbsio dll LPCUSBSIO library Script_File txt A default list of script files loads when the GUI opens U...

Page 29: ...n board power cycle or to remove USB2 cable from the module click the Disconnect button then click the Connect button to re initialize the LPCUSBSIO module I2C Reset Clicking the I2C Reset button all...

Page 30: ...pt 4 Script 5 Script 6 Script 7 Script 8 Loop Script Checked Scripts are executed in the order described 1 2 3 4 5 6 7 8 and going back to 1 If a specific script file entry is empty that entry is skip...

Page 31: ...ddress field The read out value is populated in the Value Hex field Write The Write button performs a write operation to the register address field The write value is loaded from the Value Hex field P...

Page 32: ...0x07 0x03 0x07 0x03 0x07 0x03 DUT 0x23 20 0x03 0x00 Bottom LCTRL 2 1 1 z EQ 9 1dB 8GHz Bottom LCTRL 3 1 OSL 950mVppd Bottom FG 2 1 1 1 0 7dB on All Channels DUT 0x2b 28 0x07 0x05 0x03 0x05 0x03 0x05...

Page 33: ...l Channels DUT 0x23 20 0x07 0x07 0x03 0x07 0x03 0x07 0x03 0x07 0x03 DUT 0x23 20 0x03 0x00 Bottom LCTRL 2 1 0 z EQ 3 0dB 8GHz Bottom LCTRL 3 1 OSL 950mVppd Bottom FG 2 1 0 0 0 7dB on All Channels DUT 0...

Page 34: ...ction 0x2B PCIe B 3 0 0x2B IC_LANE 3 0 PCIe_RX 3 0 0x2A PCIe B 7 4 0x2A IC_LANE 3 0 PCIe_RX 7 4 0x29 PCIe B 11 8 0x29 IC_LANE 3 0 PCIe_RX 11 8 0x28 PCIe B 15 12 0x28 IC_LANE 3 0 PCIe_RX 15 12 Back Sid...

Page 35: ...by customer s third party customer s NXP does not accept any liability in this respect Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and co...

Page 36: ...rol switch schematic 16 Fig 15 Front side K2 control switch schematic 17 Fig 16 Front side K5 control switch schematic 17 Fig 17 Back side K3 control switch schematic 18 Fig 18 Back side K4 control sw...

Page 37: ...are update 26 4 GUI introduction 28 4 1 List of files 28 4 2 Editing Script_File txt 28 4 3 GUI Fields 29 4 4 Interface 29 4 5 Script Files 30 4 6 Messages 30 4 7 Register Information 31 4 8 PTN3944 R...