•
Analog Clock Off (ACKOFF): When the CPU is done receiving
analog data, it turns off the analog clock by writing to 74LS138
position 7.
Note that in normal operation, all of these outputs should be active so
that a Logic Probe connected to any of these lines will flash to indicate
the presence of pulses.
The signals generated by the 74LS138 are too narrow to be used for
keyboard control. As such, they are stretched by the LS279 flip-flops
coupled to the LS165 shift register. These stretched pulses are called
CKA, DSTRA and ASTRA and drive the LS138 U24 demultiplexer which
guarantees that the three strobes will not overlap when driving the level
shifter/power circuit that drives the keyboard. The LS138 outputs 0, 2, 4
& 5 are combined by the 7407 and associated transistors to generate a
tri-level clock/data signal.
The power for this section is supplied by two voltage regulators to
p18V for the signal peak, +10V for the clock level, +5 for the
DSTR and Ground for the ASTR. The voltage regulators are driven by
the unreg21V supply, which is fused on the power supply board.
In normal operation, the clock/power line should always be active. Since
the CPU demands information from the keyboard whenever it deems it
necessary, it will be virtually impossible to sync onto this signal; however,
it should be possible to see the three distinct voltage levels on a good
quality oscilloscope.
7.3
Keyboard Data Interface
The data coming from the keyboard is both analog and digital. The
analog data corresponds to the controllers for joystick X and Y as well as
keyboard pressure. The digital data corresponds to key position.
7.3.1 Digital Data Retrieval
The digital keyboard data corresponds to 61 keys and one switch
(Fwd/Rev). Each key (and the switch0 may be either up, down or in
transition, corresponding to data voltage levels of + voltage, - voltage or
zero voltage respectively. The opamp buffer LF356 U13 buffers the
keyboard data for processing by the analog demultiplexers and
comparators.
LM311 U11 and U12 are used to detect the key up and key down
transitions. The outputs of these LM311s are connected to the CPU data
bus bit D7 using the LS125 tri-state gates U9. Selection of the key up
