Omron 8025G, Maintenance Manual

Page 1: ...J MAINTENANCE MANUAL ...

Page 2: ...8025 CRT TERMINAL MAINTENANCE MANUAL OMRON CORPORATION OF AMERICA INFORMATION PRODUCTS DIVISION 432 TOYAMA DRIVE SUNNYVALE CA 94086 408 134 8400 TWX 910 339 9341 ...

Page 3: ...36 XXX No information contained herein may be reproduced or disseminated to any person or company without the express written permission of Omron Corporation of America Information Products Division October 1 1975 U ...

Page 4: ...erates service the 8025 We have taken care to make this manual as complete accurate and under standable as possible Your comments and suggestions for increasing its quality and effectiveness will be most welcome A convenient pre addressed Publication Change Request form for this purpose is provided on the next page To receive updated materials our manual must be registered with Omron Apre addresse...

Page 5: ...Facility 1 9 1 3 5 Suppliers Warranties 1 9 1 4 Repair and Return of Equipment 1 10 1 4 1 P olicy 1 10 1 4 2 Equipment Failure 1 10 1 4 3 Non repairable Determination 1 10 1 4 4 Equipment Return Procedure 1 10 1 4 5 Packing and Packaging Procedure 1 10 1 5 List of OMRON Mnemonics 1 12 2 Installation and Checkout 2 1 2 1 Unpacking Procedure 2 1 2 1 1 Inspection 2 1 2 1 2 Unpacking 2 1 2 2 Off line ...

Page 6: ...Next Line J Key Function Keys and Indicators 3 7 I dividua1 Key Descriptions 3 7 1 A1phanumeric Punctuation Symbo1 3 7 2 Store Input Key Indicator 3 7 3 Storage Transmit Key Indicator 3 7 4 KSR Mode Key Indicator 3 7 5 Print Key 3 7 6 Store Key 3 7 7 Read Key 3 7 8 Keyboard Disabled Indicator 3 7 9 Received Parity Error Indicator 3 7 10 Frame Transmit Key 3 7 11 Local Copy Key Indicator 3 7 12 Bre...

Page 7: ...ase Characters Lower Case Characters 4 4 Card Section Descr iptions 4 4 1 Power Supply 4 4 2 CRT Display 4 4 3 Timing Control Card 4 4 4 Processor Card 4 4 5 PROM Card 4 4 6 Buffered RAM Refresh Memory Card 4 4 7 Refresh Buffer Card 4 4 8 Refresh Control Card 4 4 9 Cursor Control Card 4 4 10 Video Control Card 4 4 11 The Keyboard 4 4 12 RS 232 Interface Card 4 4 13 Terminator Card 5 Not Applicable...

Page 8: ...eplacement Procedures 7 1 Required Equipment 7 2 7 3 7 4 5 V dc Regulated Output Click Beep Volume CRT Disp1ay Adjustments 7 4 1 7 4 2 7 4 3 7 4 4 7 4 5 7 4 6 7 4 7 7 4 8 Preliminary Procedure 55 V dc B Adjust Video Gain Vertical Adjustments Horizontal Adjustments Centering Adjustments Yoke Adjustments Focus 8 Drawings CUl sor Control Display Monitor Keyboard L E D Mother Board Power Supply Proces...

Page 9: ...1 Transmit Vata BA Pin 2 10 1 2 Receive Vata BB Pin 3 10 1 3 Request to Send CA Pin 4 10 1 4 Clear to Send CB Pin 5 10 1 5 Data Set Ready CC Pin 6 10 1 6 Received Line Signal Detector CF Pin 8 10 1 7 Data Terminal Ready CD Pin 20 10 1 8 Ring Indicator CE Pin 22 10 2 ISO Character Assignments 10 2 1 Mne onics and Their Definitions 10 2 2 The ASCII Code 10 2 3 Tape Track Assignments List of Abbrevia...

Page 10: ... connectors 8025 CRT terminal keyboard 8025 CRT terminal block diagram Example of upper case character H Example of upper case character V Example of lower case character h Example of lower case character p Power supply block diagram CRT display block diagram CRT waveforms Timing control card block diagram Timing control card timing diagram Timing control card timing diagram Processor card block d...

Page 11: ...flection Card CRT adjustment and test point locations Vertical linearity adjustment R109 incorrectly set Height adjustment Rl07 incorrectly set Vertical hold adjust ent RI03 incorrectly set Vertical hold adjustment Rl03 incorrectly set Horizontal width adjustment LI04 incorrectly set brightness control too high Severe misadjustment of horizontal centering adjustment R143 Linearity sleeve inserted ...

Page 12: ...n register XC4 input output parameters X v matrix switches and their functions LED Keyboard indicators Inputs and output states of command decoder X02 p 1 4 2 8 3 3 3 1 4 9 4 3 4 4 4 4 4 5 4 6 4 6 elf pi 1 1 2 1 3 1 3 2 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 4 10 4 11 Status bits 4 7 4 12 UA CLK Configuration for various baud rates 4 13 Program re tart addresses provided by El E6 jumper options 6 1 S...

Page 13: ...eceived data 1 1 1 Functional Description The 8025 CRT Terminal is a computer system designed around an internal 1IIi croprocesor CPU interfaced to memory The CPU allows the terminal to be easily adapted to many applications and functional routines without hardware changes In addition data bus organization permits the 8025 to be interfaced to a wide selec tion of peripherals such as communications...

Page 14: ...cal Description External Figure 1 2 shows tha ou side of the 8025 tained within a two piece free standing plastic housin Its design make the unit ideal for table or desk top installation external equipment and primary power is done at the rear panel need to be removed to take off the op sectlon of the housing removed the internal assemblies are easy to reach The terminal is con size weight and Int...

Page 15: ...in Figure 1 4 For simplicity the diagram shows internal communications taking place over only one data address bus AUXILIARY MODEM STORAGE PRINTER RS232 RS232 RS232 INTERFACE INTERFACE INTERFACE t t DATA ADDRESS BUS t IKEYBOARD I RAM PROM MICRO PROCESSOR REFRESH PROGRAM CPU MEMORY MEMORY CRT DISPLAY Figure 1 4 8025 CRT terminal simplified block diagram 1 3 ...

Page 16: ... is a function code e g carriage return the CPU executes the instructions to move the cursor to the start of the line in refresh memory A data transfer from an I O interface is performed in the same manner In this case the interface intercepts the poll and identifies itself to the CPU The CPU enables the transfer and processes the data as if it came from the keyboard Assume the CPU has data for th...

Page 17: ...c Upper case and numerics 7 x 7 dot matrixf 14 x 7 effective dot matrix with 1 2 dot shift provides more natural looking charactersf lower case 7 x 9 dot matrix 7 x 7 displayable 0 125 x 0875 H x W 80 characters line 24 lines frame 1 920 charac ters frame max displayable or 80 characters line 12 lines frame 960 characters frame max display able ASCII 64 or 96 characters RAM 1 024 bytes PROM or ROM...

Page 18: ...bit character 110 baud 10 bit character all other rates Parity odd even or none switch selectable RS 232 asynchronous 1 200 baud standard 110 300 1 200 1 800 2 000 selectable by internal jumper option Auxiliary Storage Interface RS 232 asynchronous 1 200 baud standard 110 300 1 200 1 800 2 000 selectable by internal jumper opt ion Operating Features N Key Rollover Acoustic Feedback No data loss wh...

Page 19: ...lectrical Input Power Mechanical Size Weight Mounting Cabinet Environmental Temperature Humidity Altitude 115 V 11 5 V ac 59 61 Hz 300 watts 16 height 17 5 width 23 depth 50 lb Free standing Plastic beige finish Operating 5 C to 40 C ambient Storage 40 0 C to 65 C 5 to 80 noncondensing 10 000 feet maximum 1 7 ...

Page 20: ...curred during field repair or damage as a result of not fOllO proper preventive maintenance procedures All parts and labor will be provided free of charge for three 3 h at the OMRON designated facility see Paragraph 1 3 4 with shipping being pa lti n both directions by the customer The custo er has the option of returning either the complete terminal individual assemblies or components All items w...

Page 21: ...d before the work starts 1 3 4 Terminal 1 3 5 OMRON Designated Facility The following facility is authorized to repair the 8025 CRT OMRON Corporation of America Information Products Division Field Service Department 432 Toyama Drive Sunnyvale Ca 94086 Suppliers Warranties Vendor supplied subassemblies and units used in the 8025 CRT Terminal which are covered by supplier warranties are as follows I...

Page 22: ...ite or using communicatio media will prepare the appropriate Merchandise Return Authorization Form No MRA 83 001 This authorization must be individually numbered It must properly iden tify the non repairabl _equipment by description part number and serial number The reason or reasons for return must also be stated in adequate detail A sample Merchandise Return Authorization appears on page 1 11 A ...

Page 23: ...INFORMATION PRODUCTS DIVISION ATTACHED TO THE SHIPPING CRATE 1 SHIP PREPAID TO u s SHIPMENTS OMRON CORPORATION OF AMERICA INFORMATION PRODUCTS DIVISION 432 TOYAMA DRIVE SUNNYVALE CALIFORNIA 94086 MRA Authorized by ITEM OTY PART NO 1 1 99 399 001 EX U_S_ SHIPMENTS ION 501 REASON FOR RETURN _ LD QJ le s L nnuo t t I t tr au nuSiIIDJ LJL tt ______________________ AUTHORIZED BY Government tlarketing N...

Page 24: ...S 232 signal used by modem RS 232 signal used by modem Character generator input bits 8 bit ASCII code Clock ready synchronous 8008 Ready with IC clock Cle r F clears video attribute register on Video Control card at end of each scan line Indicates next line shift register is loaded Composite blanking signal Indicates CPU is using memory busses Clock pulse Keyboard encoder clock at H40 rate CPU re...

Page 25: ...ck periods 5 36 usee Timing signal 16 character clock periods 10 72 usee equals horizontal blanking time Timing signal period equals 1 3 of horizontal scan line 21 44 usee Timing signal period equals 1 2 of horizontal scan line 32 16 usec _ Basic timing signal provides reference for all terminal timing signals Horizontal line 15 000 Hz 63 32 usec horizontal frequency Timing signal at scan line rat...

Page 26: ...gnal generated whenever outputs from video counter and cursor position register are equal used to generate cursor Detection of blank character in row 1 e blank memory Output enable resets DSO and enables Keyboard output register for next key depression 06 output of CPU during T2 state one of two bits that define CPU cycle type 07 output of CPU during T2 state second of two bits that define CPU cyC...

Page 27: ...rol of memory bus SRINH Shift register inhibit controls loading of display shift register in half line mode STAT Status decode of CPU I O command INP2 SYNC Output of CPU indicates CPU is on second half of a timing state T2 SYNC Second hilI of CPU T2 timing state T3 Early T3 timing state synced with IC CLK T3 SYNC Second half of CPU T3 timing state UA ClK Universal asynchronous clock clocks transmi...

Page 28: ...attributes etc V DRIVE Vertical drive V SYNC Timing signal at frame rate used to drive scan circuits in monitor same as V DRIVE WAIT CPU timing state indicates READY was low prior to end of T2 state WAIT SYNC Second half of CPU WAIT state 01 02 Timing signal that provides timing reference for all data trans fer on memory busses 1 16 ...

Page 29: ... unpack and test the terminal upon receipt Terminal installation should be made as outlined in this section 2 1 UNPACKING PROCEDURE 2 1 1 Inspection Before unpacking the terminal inspect the shipping container for signs of Possible damage to the unit during transit 2 1 2 Unpacking Set the crate Right End Up and use a knife blade 1 4 or less long to open the top of the crate Save the shipping conta...

Page 30: ...Proceed with installation if the terminal is operating correctly Should the terminal not operate correctly first check that line voltage is present and the fuses are intact Then remove the cabinet and make an internal inspection Cabinet Removal To take off the top of the cabinet remove the five screws three on the front two on the back as shown in Figure 2 1 and Figure 2 2 Lift the cabinet top str...

Page 31: ... these are Regulator Card Cursor Control Card Video Control Card Refresh Buffer Card Timing Control Card Refresh Memory Card Refresh Control Card Processor Card PROM Card RS 232 Interface Card Auxiliary Storage RS 232 Interface Card Printer RS 232 Inter face Card and Terminator Card CAUTION MOS ELEMENTS USED ON CIRCUIT CARDS ARE EASILY DAMAGED BY STATIC DISCHARGE ALWAYS HANDLE CARDS SO THAT ANY DI...

Page 32: ...INSTALLATION AND CHECKOUT SECTION 2 Figure 2 4 Printed circuit card locations Figure 2 5 Monitor Deflection Board connections viewed from top of terminal 2 4 ...

Page 33: ...at line top connector connects it to the Baud Rate Switch mounted on the rear panel of the terminal A l6 conductor flat line just below the Baud Rate cabte connects the card to J201 mounted on the rear panel of the terminal 4 The cable on the far left a l6 conductor flat line connects the Cursor Control Card to the keyboard This cable is routed along the right side of the terminal viewed from fron...

Page 34: ...ach flat line connector is labeled with pin numbers on the back Pin I should be inserted into pin 1 on the socket If all cards are properly installed interconnect cabling is correct and there is no visible damage replace the cabinet top and the screws Figure 2 7 Flat line connector configurations ...

Page 35: ... the On Off Switch all the way up When the raster appears reduce brightness until the aster disappears but characters are visible 6 Allow the terminal to operate for a few minutes Until the raster ap pears on the CRT be alert to any abnormal sounds or odors If you detect any turn the terminal off and refer to paragraph 1 3 1 in Section l 7 Check out all keyboard functions e g cursor and screen mov...

Page 36: ...MINAL REAR PANEL CONNECTOR CONNECTS TO J201 Communications modem J202 Auxiliar storage J203 Printer J206 117 V ac line RS 232 Speed Adjustment The Auxiliary Storage and Printer RS 232 interface cards are set for 1 200 baud parity off The speed for these cards can also be set for 110 300 1 800 and 2 000 baud If a speed change is required refer to Section 7 2 4 ON LINE CHECKOUT Connect the 8025 CRT ...

Page 37: ...mmended setting is one that makes the screen easy to read and comfortable for the eyes Be sure to eliminate the raster 3 1 3 Baud Rate Switch The Baud Rate switch is located on the rear panel of the terminal This Switch sets the transmission rate for the modem interface primary RS 232 Inter face Card Rates of 110 300 1 200 1 800 and 2 000 baud are selectable with this control NOTE Terminals with 2...

Page 38: ...l in forms and in general readily converse with other equipment in a data communications system 3 3 AUDIO INDICATORS Audio indicators provide a secondary means through which the terminal com municates specific information to you Two such indicators are built into your 8025 terminal a click sound and a beep sound 3 3 1 3 3 2 The Click Sound A click tells you that the terminal accepted a key stroke ...

Page 39: ...es KSR and ASR 3 5 1 KSR Mode In KSR keyed send and receive mode the terminal operates as a basic character by character key entry device Each character entered on the keyboard is transmitted immediately to the communications line If the character is dis playable it is also entered onto the screen Displayable data received from the communications line is also displayed on the screen and Tay be int...

Page 40: ... 6 3 Numt ri c Pad Keys Some terminals have a numeric pad shown in Figure 3 1 These keys dupli cate the numerical comma and period decimal point keys in the typewriter group ing That is striking a key in the numeric pad has the same effect as striking the corresponding key in the typewriter group 3 6 4 Escape ESC ana Control CTRL Keys The escape ESC and control CTRL keys are each used with one or ...

Page 41: ... Indicator Pressing this key shifted or unshifted to turn the indicator light on activates the storage transmit function and disables the keyboard KEYBOARD DIS ABLED indicator on RESET and STORAGE TRANSMIT remain enabled A record in the auxiliary storage is displayed on the screen and also transmitted to the host Pressing STORAGE TRANSMIT shifted or unshifted to turn the indicator off switches the...

Page 42: ...drive just completed a read command READ Key Pressing READ shifted or unshifted transfers data from the auxiliary storage to the CRT screen and disables the keyboard Data in storage will be read until a stop read command is transferred or the end of file is encountered on the medium The exact sequenc depends on the characteristics of the storage device 3 7 8 NOTE e host must supply the start and s...

Page 43: ... data entries are sent only to the communications line 3 7 12 BREAK Key Pressing this key places a 200 250 millisecond space on the communications line This key functions the same as the interrupt or attention key on other erminals 3 7 13 RESET Key This key is used to perform the input out and master reset operations des cribed in paragraph 3 8 3 3 7 14 SCREEN ERASE Key Pressing SCREEN ERASE shift...

Page 44: ...irst CR entered to the end of the line 3 7 22 Delete DEL Key Striking DEL generates the ASCII seven bit delete DEL character 3 7 23 Backspa e BS Key Striking BS moves the cursor one position to the left and transmits an ASCII backspace to the communications line 3 7 24 Cursor Control HOME and Arrow Keys Six keys control cursor movement They are HOME and the 5 keys with arrows Striking the HOME key...

Page 45: ...ON OFF j I t B R J G H T Figure 3 1 CRT terminal keyboP eJ SECTION 3 w 3 9 ...

Page 46: ...s When the terminal is turned on it automatically sets to ASR mode To turn the terminal off press down on the lower end of the ON OFF itch It is not necessary to reduce the brightness You can leave the terminal on if ypu wish but turn the BRIGHTNESS control down dark screen to extend CRT Ii fee 3 8 2 Clear Reset Functions I O Reset Press CTRL and RESET at the same time to stop all input out put I ...

Page 47: ...rt of text STX b End of text ETX c End of transmission EOT d Enquiry ENQ e Acknowledge ACK f Bell BEL g Backspace BS BS h Horizontal tab HT TAB i Line feed LF LINE FEED j Vertical tab VT k Form Feed FF 1 Carriage return CR CR m Shift out SO n Shift in SI 0 Data link escape OLE p Device control 1 DCI q Device control 2 DC2 r Device control 3 DC3 s Device control 4 DC4 t 3 12 ...

Page 48: ...idle sm v End of transmission block ETB w Cancel CAN x End of medium EM Y Substitute SUB z Delete DEL Escape ESC ESC File separator FS I Group separator GS Record separator RS unit separator US DEL Clear screen SCREEN ERASE Master clearl SHIFT RESE T I O reset RESET Frame transmtt FRAME TRANSMIT Next line J Store Input on STORE INPUT light on Storage transmit on STORAGE TRANSMIT light on 3 13 ...

Page 49: ...generation in the 8025 terminal contd SPECIAL CONTROL ACTION CODE FUNCTION SEQUENCE KEY CTRL plus KSR mode on KSR MODE light on Print on PRINT Store on STORE Read on READ Local copy on LOCAL COpy light on Local copy off LOCAL COpy light off Break BREAK 3 14 ...

Page 50: ...rol Card to blank out sweep retraces on the CRT display as well as to reset part of the video counter on the Cursor Control Card Circuits on the Timing Control Card also decode CPU generated I O command signals for distribution to the Cursor Control and RS 232 Interface Cards The timing control card also contains the power on clear POC generator Whenever power is applied to the terminal this circu...

Page 51: ...stored in the LED latch and made available to the Keyboard on the LED Data Channel Two SO character shift registers provide refresh data over the CG Data Channel Data from the refresh memory may be used either by the processor or by the Refresh Memory for screen refresh In either case control signal RA enables the RM gate to allow passage of data on the RM Data Channel The half line gate remains e...

Page 52: ...isplay In the second the video is mixed with the comp sync signal CS for use by an external display Video modification data from the shift register on the Refresh Buffer Card is stored in the video modification register The video modification logic decodes the register outputs video status data on the CS Data channel and the other input signals shown to produce modification commands These commands...

Page 53: ...es require data transfer When the POLL command arrives at the keyboard interface and the DSO signal is present the interface does three things 1 prevents further propagation of the POLL 2 selects itself for the next data transfer to the CPU and 3 identifies itself by putting the keyboard address on the AData Bus Upon receiving the keyboard address the CPU responds with another I O com mand 100 whi...

Page 54: ...eo modification reg ister on the video control card 3 outputs from the register are decoded by the video modification logic and 4 the logic output alters the video signal to dis play black on white until ither the next video modification character arrives or the end of the line is reached Finally let s assume the NEW LINE key is struck After determining that the character is nondisplayable the CPU...

Page 55: ...minal card cage has numbered slots for up to 17 cards The first 7 slots are occupied by basic function cards with slot 7 being used for the basic processor CPU Slot 8 is generally used for the program card which may be a PROM ROM ROM PROM or PROM RAM For some configurations the DMA processor must be lo cated next to the CPU in which case the program card is moved over to slot 9 the wiring of slots...

Page 56: ...R A E r RS232 INTERFACE CARD 3 EACH 8 L T_ SECTION 4 H EY vfDI l1 _ DATA 1 1 4 GAT I AODIIlq I Olin IERROR 1 LATCH I MA DATA BUB I I C I I CE C Cf __ SA _ CA I I CD IC ___ f i O H I T H t T f H T CHAR cm l 1 1ADDRESS l T R _ OIJNreR 1 1 I COUNT 1 _I r RA U iCROL 1JD F U L RM DA I1C CH I I N El A O A T A B U S I YIDEO GAT l CONTRO LoolC 1 cs DATA CHANNEL I v r t VIDEO I U OAtV TO CIIT 0 r CDMPOSln ...

Page 57: ... III c c c u 0 lIS III tfI III III III III 1 1 lIS N rf SIGNAL Q Q Q Q 2 0 8 rf 0 rf u 1 1 1 1 III N 5 MNEMONIC S 0 j 4 j 4 j 4 C 1 1 t rf 1 1 Q rf 1 Q E t jl jl Jl u H E t u Timing Control COMP BLNK X X CURS LINE X X EOP X EOR X X H4 X X X X H8 X HIO X H2O X X X H40 X H80 HF CLK X H SYNC X lOB X 100 X X poe X X X 4 POLL X X POS TIME X X RATE X X X READ CLK X RS CLK X SET LDFF X STAT X X VI X V2 X...

Page 58: ...l c c c u 0 lIS Ul g Ul Ul til til lIS N c SIGNAL QJ QJ QJ QJ g 0 8 M l 0 u E Ul N s B MNEMONIC e 0 14 1 11 1 14 1 t I 0 QJ QJ B QJ lQ c QJ Eo C c l l H Eo u Timing Control V SYNC X X l X X r 2 X X X Processor BDBO X X BDBl X X BDB2 X X BDB3 X X BDB4 X X BOBS X X BDBG X X BDB7 X X CPU BUSY X CPU R w X IC CLK X X I O X X X X MAO X X X MAl X X X MA2 X X X MA3 X X X MA4 X X X MAS X X X MAG X X X MA7 ...

Page 59: ...3 j l C IJl c c c u I l 0 II IJl g IJl til IJl IJl 1 1 II N I 0 SIGNAL Q CII CII CII 2 0 8 M j l 0 0 0 u E 1 1 1 1 1 1 IJl N 3 MNEMONIC IS 0 j I j I j I I l 0 C 1 0 I l CII CII 0 3 Q I Q E Il Il 0 0 U H E U Processor MAl2 X X X X MAl3 X X X X MAl4 X X MAIS X X PC6 X PC7 X WAIT X PROM ADBO X X ADBI X ADB2 X ADB3 X ADB4 X ADBS X ADB6 X ADB7 X X X Refresh Memory RMO X X X RMI X X X RM2 X X X RM3 X X ...

Page 60: ...OURCE u 0 0 U H s jJ 0 III t t t u 0 lIS III III III III III lIS N c 0 4 SIGNAL CP CP CP CP 2 0 8 M jJ 0 4 Q 0 4 U III N s e MNEMONIC f l 0 II l 0 0 4 CP 0 4 s CP c ell 8 Po Po u lo H 8 U Refresh Buffer ADB3 X ADB4 X ADBS X ADB6 X ADB7 X X BEEP BLANK X BLINK X CGO X CGl X CG2 X CG3 X CG4 X CGS X CG6 X CG7 X CLRF X CSO X CSI X CS2 X X CS3 EXT ADRS X INHLD X LCLSB X LCMSB X LITE 1 X LITE 2 X LITE 5 ...

Page 61: ...0 0 f SOURCE u 0 8 u t1 4J a III c c c III 8 III III III III ttl N 001 SIGNAL CD CD CD CD 2 51 8 M 4J C U N B MNEMONIC lEi 0 t1 a 5 CD B CD CD Eo Pol Pol l Eo Refresh Buffer LITE 10 X LITE 11 X LITE 12 X LOAD F X SR COUNT X Refresh COntrol CNT 80 X MAO X MAl X MA2 X MA3 X MA4 X MAS X MA6 X MA7 X MA8 X MA9 X MAIO X MAll X MAl2 X MAl3 X REF R W X RDO X RDI X RD2 X RD3 X RD4 X RDS X X RD6 4 13 ...

Page 62: ...0 SOURCE u 0 0 U 0 H I j I III s s s u 0 lIS III g III III III III lIS N c SIGNAL cu cu cu cu 2 0 8 M j I 0 u f III N I e MNEMONIC e 0 11 1 11 1 11 1 0 0 t cu cu cu I cu c cu 8 Ilo Ilo u H 8 U Refresh Control RD7 X SRINH X UPDATE X Video Control VIDEO X Cursor Control ADBO X ADBI X ADB2 X ADB3 X ADB4 X ADBS X ADB6 X ADB7 X X CP MATCH X X OE POLL X RPT X SPKR X Keyboard DSO X KDBO X KDBI X KDB2 X K...

Page 63: ... tJ Ul til til til III N 0 1 s Ql Ql Ql Ql 2 0 M J 0 1 0 SIGNAL 0 1 u til N j e MNEMONIC e 0 4 1 4 1 4 1 0 0 fJ 0 1 Ql Ql Ql 0 1 j Ql s Ql Eo Il Il p p p u H Eo U Regulator 5 V Reg X X X X X X X X X X 12 V Reg X X X 12 V Reg X X X X X Power Supply 80 V Unreg X 6 3 VAC X RS 232 Interface ADBO X ADBl X ADB2 X ADB3 X ADB4 X ADB5 X ADB6 X ADB7 X 0 BA CA Used By Modem CD r I I I I T POLL Propagated On ...

Page 64: ... appears in the register upon completion of 100 or lOB 100 Froduced by INP 1 within CPU With the 100 command the contents of trre CPU s A register becomes available to the device and the device may specify the new contents of the register 100 also causes the device to deselect itself Every POLL is followed in succession by an 100 tc prevent system lock up that is only one device at a time can be s...

Page 65: ... the card descriptions presented later in this section The CRT screen can be thought of as a large matrix of small light elements or dots that can be turned on and off In this context the overall video present ation is made up of light and dark dots The basic display format for the 8025 Terminal is 80 characters per line with a maximum of 24 line per frame page Thus up to 1920 characters can be di...

Page 66: ...No dot information is contained in the eighth line L 7 address Ill and no dots ever exist in c o through C 2 Incrementing L 7 back to L O makes the ninth line L 8 dot information identical to L O For this group of characters however L 8 dot information is blanked out and does not appear on the CRT screen COLUMN LINE o 2 3 4 5 6 7 8 9 ADDRESS CHARACTER I NFORMAT I ON LI E oooe oooooe 000 oooeoooooe...

Page 67: ... control dot is never used in L O for this group of characters This feature makes the characters displayed in this group more natural looking by creating an effective 7 x 14 dot area in an actual 7 x 7 dot area COLUMN LI NE o 2 3 4 5 6 7 8 9 ADDRESS CHARACTER INFORMATION lI E oooe oooooe 000 oo eooooe 0 001 2 ooooeoooeo 010 3 oo oeooeo a 011 4 ooooo eoeoo 100 5 oo ooeeooo 101 6 000000_000 110 7 00...

Page 68: ...t blanked Figure 4 4 Example of lower case character h Characters With Descenders g j p q and y Using p as an example Figure 4 5 shows how lower case characters with descenders are formed Again the same basic operations as for the other lower case characters apply For this group however a control dot in C 2 L O in addition to producing the half dot shift in dicates that dot formation in L O will b...

Page 69: ...rement to 000 Yes same as L O but unblanked e il l uminated dot control dot Figure 4 5 Example of lower case character p 4 4 CARD SECTION DESCRIPTIONS 4 4 1 Power Supply Except for the de voltages used in the CRT Display the Power Supply provides all voltages required by the 8025 CRT Terminal Block Diagram Analysis As shown by the simplified block diagram in Figure 4 6 the Power Supply consists of...

Page 70: ...ription Refer to schematic diagrams in Section 8 o With the terminal on off switch closed primary power is applied through fuse F201 to the fans assembly and to the primary windings of step down transformer T2 Power is also applied via fuse F202 to the primary of step down transformer TI One secondary winding 10 11 of T2 supplies 6 3 V ac for the display CRT filament via J61 3 4 The 80 V dc output...

Page 71: ...ections video vertical sweep hor izontal sweep and low voltage regulator An adjustable closed loop voltage regulator provides a constant output to all stages in the CRT Display The X ray protection circuit prevents any X radiation due to line voltage surges or regulator failure Under those conditions the circuit disables the horizontal drive multi vibrator Video inputs are amplified and inverted b...

Page 72: ...erminal keyboard The vertical sweep section is made up of QlOl Ql02 and Q122 QlOl a programmable unijunction transistor with its associated circuitry forms a relaxation oscillator operating at the vertical sweep rate Timing is deter mined by RC network RI06 108 CI03 and CI04 When power is applied Cl03 and CI04 charge toward SS V dc through RI06 and Rl07 The charging rate is set by the time constan...

Page 73: ...rity adjustment determines the slope change rate Consequently emitter follower Ql02 supplies a suitable sawtooth waveform of about 5 V amplitude to the base of Q122 The vertical output stage Q122 operates as a class B amplifier with out put transformer coupled to provide a proper impedance match with the yoke L124 During retrace time a large positive pulse typically 300 V is developed across T102 ...

Page 74: ...tive gate is differentiated by C12l and R153 to trigger the horizontal drive one shot Ql14 Ql15 In the staple state o the horizontal drive one shot Ql14 is held at satur ation low state by virtue of the base current flowing through RlS2 and CR109 Consequently Ql15 is at cutoff high state When the negative going differentiated pulse from Ql12 is applied to the base of Ql14 Ql14 is driven to cutoff ...

Page 75: ...lse several microseconds in d ration several hundred volts in amplitude and in the form of a half cycle sine wave is developed by the combined inductance of L124 and TI03 plus Cl 7 The peak inductive energy stored in L124 during the sweep time is then transferred to e127 and the distributed capacity in L124 During this cycle the beam is returned to the center of the screen Capacitor C127 and the d...

Page 76: ...ainst triggering of the hori zontal output transistor Q123 by random drive pulses during turn on or turn off Normally several ac cycles are required after turn on to bring the 55 V dc bus up to level By virtue of the component values selected for Ql09 Qlll and R15l the delay one shot will not trigger until the regulator voltage exceeds approximately 30 V dc This dc voltage is adequate to provide s...

Page 77: ...on circuits however may be much greater than the average current even though electrolytic capacitors are used across the 55 V dc line 4 4 3 Timing Control Card The timing control card supplies the basic clock and timing signals for the 8025 CRT terminal TIlis card is also the source of a power on clear signal and the four input output signals used in the terminal Block Diagram Analysis As shown by...

Page 78: ...OC pulse on pin 72 The balance of the schematic is devoted to the generation of timing sig nals for the terminal Ql Q2 and their related components form a crystal controlled master clock at 29 9S2 MHz Its output is coupled through XBI 8 to XAI II which divides the clock frequency by two to supply HF CLK high frequency clock HF CLK 14 976 MHz is applied to the character clock divider XOS RS clock d...

Page 79: ...T fo VIDEO CONTRtL CARD HORIZONTAL FREQUENCY 16 6 J CHARACTER CLOCK 1O 1 82 CLOCKS r 1 MAg MAIO POLL 100 L L L H H L H L L H H H H H H H VSYNC HSYNC TO VIDEO COMPOSITE 2 CHARACTER r SOR SYNC DELAY COMPOSITE BLANKING CONTROL t CARDS 0 HORIZONTAL r POSTIME BLANKING INVERTER GENERATOR l ROW RATE VERTICAL CARRY CLOCK COUNTER CLOCK 13 12 TO VIDEO CONTROL CARD OTHER TIMING r LOGIC READ CLOCK Figure 4 9 ...

Page 80: ...nd the optional 40 character per line display H BLNK is inverted by XCS 12 to become POS TIME H BLNK is also used for the J K inputs to the XBS 2 flip flop which produces the horizontal component of composite sync COMP SYNC The negative edge of H40 sets XBS Eight character periods later it is reset by HI60 at XBS 13 to produce a 5 36 usee pulse The out put on XB5 2 is OR gated by XE2 ll to the 20 ...

Page 81: ...THEORY OF OPERATION SECTION 4 HFCLK Hl H2 H4 HiJ H9 Hl0 _____ C H4 _ sEnti F F 02 t 01 0 cNf ____ READ CLOCK _______ F 1gure 4 10 TiC ontrol card timing d 1agram 4 33 ...

Page 82: ...H100 H320 4 H LINE POS TIME f HBLNK H DRIVE HSVNC Figure 4 11a T1m rg con Ol card t1m1ng d1agram SECTIOt 4 4 35 ...

Page 83: ... Vl V2 V4 _______ 1 va 4 J V10 4 4 EaR 4 CURS LINE _________4 _______ J RC EOP V DRIVE ______________ ______________ __________ J COMP SYNC 1 CaMP BLANKING Figure 4 11b Timrffg control card tlndng diagram SECTIm 4 4 37 ...

Page 84: ...lanking UND BLNK signal The remaining signals generated on the Timing Control Card are cursor line CURS LINE end of page EOP and set load flip flop SET LDFF Cursor line is produced by XDI pin 6 whenever VI and V2 are low at pins 5 and 6 of XEl and V8 is high EOP is generated by decoding RC VIO and EOR in XF2 6 A 63 6 usec output pulse with a 60 Hz rate appears at XF3 8 at the end of every 24 chara...

Page 85: ...signal replaces Tl when CPU is interrupted STOPPED Indicates CPU received a HALT instruction WAIT Indicates CPU READY line was low prior to end of T2 cycle Data on the A Data Bus comes in to the CPU through the input drivers dur ing T3 A precharge circuit decreases the input rise time Output data from the CPU is placed on the B Data Bus during T3 and on the MA Data Bus during T2 and Tl or TIl In a...

Page 86: ...estart the CPU during T3 Flip flops XA6 and XA4 are reset at the end and start of T3 at pins 1 and 4 respectively A PaC initiated in errupt is accomplished in the following manner When power is applied to the terminal pac goes high and is inverted by XBS IO to reset flip flop XA3 at pin 10 The next low RATE pulse at pin 9 of XBS sets the XA3 flip flop at pin 9 Since RATE occurs at 5 pps it produce...

Page 87: ...d into the XD2 and XD4 registers to provide the least significant eight bits of an address The most significant six bits are loaded into XD3 and XDS during T2 Data out of the registers is placed on the MA Data Bus via drivers XE4 XES and XFS These drivers are also enabled when the CPU can transfer data in either direction Note that the two most sig nificant bits located into XDS contain CPU cycle ...

Page 88: ...TE COMMAND Tl SYNC WAIT SYNC READ GATE CPU BUSY ADDRESS IN DATA OUT 1 33 sec J 11 I j I I r12 1 I 21 I 22 I I I I Figure 4 13 Processor card CPU tlndng dlagram I 11 I I 12 I 11 r l I 22 I 1 I I I I I I I I SECTION 4 1 J 12 T J 11 J 12 1 21 r J 21 h J 22 J j1 I 1 yi i ii j J I I I 0 i I J 1 I I 4 43 ...

Page 89: ...and it partially enables all of the chips Assuming the sector gate is satisfied the chip selector supplies the second enable input to the PROM chips specified on MAS II This second enable in put plus addressing on MAO 7 defines the mem ry location of the data to be read out on the A Data Bus Circuit Description Refer to Schematic diagram 96 434 XX in Section 8 The maximum capacity If fewer than 4 ...

Page 90: ... inputs pin 13 of two PROM chips e g the output at XES l is applied to PROM chips XBI and XDl A low input at as selects the two chips for reading The lower four and higher four data bits are stored in the XB and XD series PROM chips respectively Eight bits of address MAO 7 plus a low input at both as and C52 allow the data stored in the two chips to be read onto the A Data Bus Table 4 3 gives PROM...

Page 91: ...and 12 header XF6 and NAND gate XE6 8 fonn the address sector gate The four most significant address bits fA12 15 are wired on the header to define the address sector for the card For the card shown jumpers EI EI6 E3 E14 E5 E12 and E7 EIO are 1n place to define address sector 3 addresses 340008 to 377778 For any address between 34000S and 377778 MAl2 and MAl3 are high MAl4 and MA15 are hard wired ...

Page 92: ... in Figure 4 16 Video status data is stored at address 377718 in the refresh memory When called from memory at the end of each page the data_is placed on RMO 3 in order to update the video status latch The BLANK and CSO 3 outputs control block and underline cursor video on off and control character blanking RMO 7 LED LATCH rrRMO 3 VIDEO N STATUS LATCH IiI FAo 1 RM GATE A DATA BUS ICCll MA9 1 110 a...

Page 93: ... for an entire character row SO characters is loaded into the re fresh shift register from the next row shift register at the end of every character row The refresh register functions as a la cycle recirculating memory to supply refresh data for the video display on CGO 7 When data has been transferred to the refresh register data for the following character row is read out of memory and loaded in...

Page 94: ...produced by the output on XA6 3 When the CPU is not busy CPU BUSY is low the refresh buffer takes every other available bus cycle XA6 3 is low for one 2 period and is then set high for thf next 2 period to generate SR COUNT As stated above data in XE3 and XD3 is loaded at the end of each charac ter row into the refresh shift register XE2 and XD2 with loading controlled by the EOR end of row signal...

Page 95: ...___i _4 1_ 1 XDl 6 0 UPDATE COUNT80 4 L_I____ _ _ 1 1r 1r I I I I I I 1 I I I SRCOUNT ___________ __________ _______ ________ 4________ TYP REGISTER CLOCK _____________ _ 4_ 4_ t_ t_ t j lCMSB IL _ i _ LCLSB _ _ _4 _t _ _t t 1 REGISTER 2 CLOCK REGISTER 2________ _______ __________ _________ 1___ 1 1 LOAD Figure 4 17 Refresh buffer control card tIm1ng dIagram 4 51 ...

Page 96: ...POSITION tiME REGISTE R 2 IUWI IoIoI IoIIoI IoIIILIIoII uw CLOCK EaR EOP ________ __________ UPDATE REGISTER CLOCK 80 CLOCKS 96 CLOCKS F1gure 4 l7b Refresh buffer control card t1rndng d1agram 80 CL LOCKS 80 CLOCKS 80 CLOCKS i SECTIOf 4 4 53 ...

Page 97: ...is decoded in XCS and XD6 the character n CGO 7 is a video modification character rather than a displayable character The three least significant bits of the character define the modification e g dim blink 1o be made to the video presentation LOAD F is gated at the character rate H8 on XES 5 as long as an HLL exists LOAD F is used to load the video mod ification register on the video control card ...

Page 98: ...s from 0 to 15 and sup plies a carry output to the second stage The second stage preset to a count of ten at the end of every character row counts 5 of the first stage carry outputs to generate CNT BO The character counter thus counts the number of character positions in a row Outputs from the character counter are decoded in the 40 character de coder to generate an output at the 40th character po...

Page 99: ...he last S loca tions in memory are being addressed during vertical retrace XA4 6 remains low until cleared at the end of the character row input on XCl 2 or the end of the page input on XCl 13 Thus SRINH is high during the loading of the characters for the first Qalf of the character row and low during the last half When SRINH is low XB4 3 and 6 are low to inhibit the address gates XE3 XE6 and mem...

Page 100: ...nto XCS and XC6 At the count of II bit A goes high Con sequently XA3 8 goes high and XA3 ll goes low to load the second byte of page base into XC3 and XC4 The remaining circuit on the refresh control card generates REF R W This signal is CPU R W or EXT WRT clocked with 01 EXT WRT is used by an external device to write data into memory 4 4 9 Cursor Control Card The cursor tontrol card the next char...

Page 101: ...t that enables the KDB to ADB gate also triggers the click multivibrator The pulse output from this one shot is amplified to drive a speaker mounted on the keyboard The click one shot is triggered every time a key on the keyboard is depressed A programmable beep feedback is controlled by the BEEP input to another one shot multivibrator The output pulse from this one shot is amplified to turn an os...

Page 102: ...ive NOR gates XCS XD5 and XES function as the comparat The top five gates compare row information while the bottom seven compare column information When all counter outputs are equal the comparator produces a high output MATCH The keyboard interface circuitry cOJ sists of the KBD to ADB gates with their related contPol logic a POLL gate and a repeat signal generator The sequence by which data is t...

Page 103: ...nother DSO two clock pulses later The outputs of the second and third stages of the register XE2 9 and 6 are decoded by NAND gate XC2 3 to inhibit triggering of XDI during the two clock pulse perjod If DSO occurs at the end of two clock pulses it indic tes that the key is still depressed and the last character transferred is repeated approxi mately 15 times per second until the key is released Sho...

Page 104: ...the corresponding 8 bit ASCII code on CGO through CG7 The line to be displayed is specified by VI V2 and V4 A paralle1 to serial converter serializes seven bits out of the character generator at the video rate HF CLK and applies the output to two video mixer amplifier channels One channel feeds the CRT display the other combines video and composi sync signals to supply a composite video signal for...

Page 105: ...gh 5 meet the selection criteria for XA2 and the bits for columns 0 1 6 and 7 meet the criteria for XA4 Table 4 6 Character generator ROM selection ROM INPUT ROM ENABLED El E2 XA4 CG5 CG6 both L XD5 6 H or both H and CG7 L XA2 CG7 L CG5 H or CG6 H but not both When line and character informati on are applied to a RO I that is en abled it puts out character data in parallel form The outputs of both...

Page 106: ...om VI V2 and Vi respectively VI t V2 and V4 are low for the first LO and ninth LS lines in the character display matrix Thus XC6 9 10 and 11 are low dur1ng LO and LS to produce a high input to XE6 13 that partially enables XE6 during these two 11nes VS is high for matrix lines LB through L7 so that XE6 6 is high during these line5 when XE6 4 is low Thus NAN gate XE6 ll is enabled only when Os is l...

Page 107: ... character or the end of the line occurs The modification character format is HLLXXYYY with YYY defining the modification e g reverse video blink etc The XX portion is available for defining software functions e g define protected fields Modification codes and their functions are given in Table 4 7 Video modification codes on CGO through CG2 are stored in XC4 a type 74175 flip flop XC4 is loaded b...

Page 108: ...S 9 With all of these low the resulting high at XCS 8 is NAND gated to a low level at XEl S This level clamps the video signal at the mixer network to ground and caus the CRT screen to go blank Blanking is also performed by the output at XEl 3 which is controlled by the COMP BLNK and BLANK inputs The video is blanked when either or both of these inputs are lo The cursor function involves the logic...

Page 109: ...tions The encoder supplies a pulse train to the X lines in the matrix When a key is depressed to connect the X output to the Y input of the encoder the X V coordinates in the matrix are defined The encoder decodes the coordinates con verts them into 8 bit ASCII encoded on KDBO 7 and supplies a DSO data strobe out Signal to the keyboard interface on the cursor control card When the data is transfer...

Page 110: ...e decoded in the encoder and converted to an ASCII 8 bit code by a ROM in the encoder Each X V coordinate can be converted into four different codes throu h the use of the shift and control keys Mode lo ic within the encoder serves as an interface between these keys and the ROM Shift and lock switches 2 or 13 and 15 respectively perform the same ftmction as the shift and lock keys on a typewriter ...

Page 111: ... 86 Special functions 53 84 87 94 Not used 12 line display terminal SWITCH NUMBER FUNCTION 2 13 Shift 14 Tab 15 Lock 28 Line feed 29 Control 42 Delete 43 Carriage return 57 Escape 58 69 Omitted 70 Not used 71 73 75 77 Cursor control 72 Not used 76 Cursor control 78 Not used 79 82 85 86 Special functions 53 84 Not used 87 9 1 Special functions SECfION 4 Remainder Special functions Alphabetic typewr...

Page 112: ...date up to 16 light emitting diodes CRI 16 These are used to provide visual keyboard indications of terminal status and or operating modes A LED is activated whenever a LED latch buffer on the refresh buffer card applies a low level to the LED cathode The diodes installed and their corresponding indications are listed in Table 4 9 Table 4 9 LED keyboard indicators DIODE ON OFF STATE INDICATION KEY...

Page 113: ... on the BA line to interrupt the external device Serial data BB from the modem is applied to the RS 232 receive control From there the data goes to the receiver where it is converted into parallel form and is then placed on the A Data Bus through the data gate Word length 5 6 7 or 8 bits is established by the word length selector The receiver transmitter also generates overrun framing and parity e...

Page 114: ...SELECTOR I CF I RECEIVE I F U CLK UAelK ul I DATA I GATt 1 I I I eCEIVE I G 8 ___ I JTRANSMITTER I lOGIC 1 TRANSMIT I I I I I l t T 8 J RESET I ERROR L J ERROR MAO 7 LATCH I I GATE UACU PO GATE INTERFACE CONTROL CIRCUITRY f POll OUT I t t ENABLE I C8 IDO BREAK 9 t MAt I ADDRESS I I I COMPARATOR ReoueST CE _I ro SEND I STATUI I GATE CQMMAND CF DECODER RECEIVER J L fUllf J TRANSMITTfM r RESET DATA j...

Page 115: ...at XD6 2 resets the outputs of the status flip flops XES to a low level The reset states for the four flip flops in XES are as fallows 1 Request to send CA flip flop QO off CA is thus low at XB6 6 2 Receiver flip flop QI off 3 Transmitter flip flop Q3 off 4 Data terminal ready CD flip flop Q4 off CD is thus low at XB6 8 Reset is also initiated by a read status command from the CPU This event occur...

Page 116: ... l causes XF6 3 to go high on the next IC CLK pulse at XF6 l2 enabling the XF5 3 gate Without an 100 the low level at XF5 3 inhi bits the received data gates XF1 XE2 at pins 2 4 12 and 10 When the CP sends an 100 XF5 3 goes high to enable the received data gates and consequently the character in XG3 is placed on the A Data Bus The high level at XF5 3 is also clocked with IC CLK and the resulting l...

Page 117: ...es five status bits on the A Data Bus Received line signal detector CF is gated to ADBO at XEl S ADBI and 2 are not used The ihput on XEl 4 derived from CB clear to send THRE and TRE is gated to ADB3 to report transmission status THRE indicates if XG3 can be loaded and TRE indicates if XG3 is transmitting a character If XEl 4 is low the trans mitter is not availabie Ring indicator CE is gated to A...

Page 118: ...REAK one shot XD6 0 1 0 0 0 1 0 1 Not used i I 0 1 1 0 0 1 1 1 1 0 0 0 3 2 Set data terminal ready flip flop XES 10 to on I 0 0 1 4 3 Set request to send flip flop XES lS to on 1 0 1 0 1 0 Set receiver flip flop XES 13 to on 1 0 1 1 2 1 Set transmitter flip flop XES 12 to on 1 1 0 0 7 6 Reset data terminal ready flip flop to off 1 1 0 1 9 7 Reset request to send flip flop to off 1 1 1 0 5 4 Reset ...

Page 119: ...counter stages XB3 and XB4 288 kHz is divided in these counters to produce a UA CLK signal for XG3 at 16 times the shift rate is applied to the RCC and TRC pins 17 and 40 of XG3 Table 4 11 Status bits STATUS BITS ADBO Receive line signal detector CF ADBl Not used ADB2 Not used ADB3 Transmitter available if Hi not available if L ADB4 Ring indicator CE ADB5 Parity error ADE6 Framing error ADB7 OVerr...

Page 120: ...REAK at XCl 4 Received data BB on J2l lS is inverted by XBS ll If CF received line signal detector is high at XBS l the data is applied to the RI input pin 20 of XG3 Data for transmission appears on the TRO output pin 2S of XG3 and goes to XB6 l3 This data is gated by XB6 ll the RS 232 driver to J2l l6 BA by BREAI at XB6 l2 A stop state high level from TRO produces a mark or low level at the BA ou...

Page 121: ...lock is also included to program restart commands Block Diagram Analysis As indicated by the block diagram in Figure 4 23 all data bus control clock and restart lines are terminated to prevent signal deterioration The location selector a strapping block provides for grounding one or more of the restart lines to specify restart commands A restart command specifies the program memory location at whi...

Page 122: ...4 13 Program restart addresses provided by EI E6 jumper options RESTART ADDRESS AFTER JUMPERS IN AN INTERRUPT APOC None standard 8 lOS E1 to E2 lOe 1 8 E3 to E4 2 8 3 8 E1 to E2 and E3 to E4 30e 3 8 E5 to E6 4 8 5 8 E1 to E2 and E5 to E6 5 8 5 8 E3 to E4 and E5 to E6 60s 7 8 E1 to E2 E3 to E4 70S 70e and E5 to E6 4 80 ...

Page 123: ...THEORY OF OPERATION OPTIONS SECTION 5 This section is not applicable to the 8025G CRT terminal 5 1 ...

Page 124: ...uipment and materials are used in preventive maintenance Triplett 310 Multimeter or equivalent Clean soft cloth Glass cleaner nonabrasive Contact cleaner e g No Noise Contact Restorer Anti corona lacquer or dope Hand tools General Procedure Whenever the terminal is serviced be sure to check its physical condi tion Visually inspect the tenninal inside and out for dust dirt etc NOTE Check inside the...

Page 125: ...rs are tight and all connectors are secure and undamaged Keyboard 1 Check keys for loose caps and switches sluggish movement intermittent operation and double stroke action two characters produced per stroke 2 Inspect the keyboard area for foreign material if service required cabinet re moval Cooling Fan 1 See whether the cooling vents are blocked with paper lint etc 2 Listen for normal fan operat...

Page 126: ...igh voltage arcing If present remove dust from all high volt lage leads and apply anti corona lacquer dope Confirm that all display parameters e g centering linearity and width are set for a normal presentation See Figure 7 3 in Section 7 Make the requir ed adjustments for normal presentation refer to paragraph 7 4 in Section 7 Clean the CRT face with a nonabrasive glass cleaner 6 2 FIELD MAINTENA...

Page 127: ...onnected FIND THE CAUSE OF A BLOWN FUSE BEFORE REPLACING IT DO NOT REMOVE OR REPLACE CIRCUIT CARDS WHEN TERmNAL POWER IS ON MOS elements are used in the terminal They are easily damaged by dis charges of static electricity Never handle circuit cards unnecessar ily Correct handling procedures are outlined in paragraph 6 2 5 Keep the terminal clean inside and out Perform routine maintenance procedur...

Page 128: ...loose or broken con nections damaged printed circuit cards scorched wires or components etc Visible troubles usually have an obvious remedy Set the Baud Rate switch at the correct position before you begin troubleshooting Isolating 1alfunctions When troubleshooting consider all complaints and symptoms together rather than individually Also be aware of possible temperature effects when isolating an...

Page 129: ...t related to the click response 3 Before replacing either the Cursor Control or Refresh Buffer however determine the probable operating status of the other three cards Re view the Theory of Operation and schematics in this manual to establish which signals on the three cards are directly or indirectly related to both the click and the beep circuits Such a review will reveal that both audio indicat...

Page 130: ... fJ QI I U N 0 0 f1l Q 1J 0 S QJ QlN N 1 1 0 S 0 t tu QJ fJ I 1 0 0 I I QJ 1J OJ I I N I z OJ I 0 Ul U p r l U p U l I r 0 Eo U A U D I B L E S Y M P TOM S Beep response inoperative X X X X Continuous beep X X X II Beep response all keys X X X X X Beep and click responses inoper ative X X Click response inoperative X X X X X Continuous click after terminal power is applied X Rapid click response X...

Page 131: ... s IJ III IJ 14 14 tl 44 S 44 s IJ u E X X X X X X X X X X X X X X X C H A R ACT E R S Y M P TOM S Constant character jitter X X X X Character jitter every key stroke X Character flicker X X Deformed character s X 6 8 SECTION 6 MALFUNCTION PROBABLY IN 0 M J 0 Ul Q E 0 c J J IJ o J U IJ s s tl M J til J IJ IJ M 0 14 0 c til 0 rUM M M s U 0 U g M s 0 0 o 0 tl J 0 s 0 Ul J U c III M III Ul 0 IJ til U...

Page 132: ...CI 0 I I 8 OM CD tj 0 N s 8 OM 0 U 0 p U u p t n I z t 0 0 CHARACTER SYMPTOMS continued No upper or lower case characters X X X Miss ng character set X Displayed character alternates between correct and incorrect character X X Character is displayed simUlta neously on two or more lines X X Display filled with one char acter X X X X o T HER DISPLAY S Y M P TOM S No raster X X X X X X Intermittent r...

Page 133: ... u OJ 00 H tl tl I I 1 M OJ M H t fJ N 1 z OJ 8 M 0 Ul u 0 Eo III J ll U III til M r 0 Eo 0 o THE R DISPLAY S Y M P TOM S continued Blank display raster present X X X X X X X X Brightness control ineffective Defective Brightness Control Garbled data display X X X X Repetitive garbled data displayed X X Only one line usually short displayed r X X X All field modification functions inoperative X X B...

Page 134: ...I Q M M M U N 0 Q III III N N 101 0 II l e II l II l 0 I u Q II M Cl 0 I I 8 M c 0 N 1 6 e 1 0 Eo p IX I u p an t r u KEYBOARD S Y P TOM S continued Keyboard mode case control in correct X X X Repeat function inoperative X X X X Single key inoperative X Multiple character display per stroke X X r Multiple character display ail or group of keys X Two different characters dis played per stroke X Wro...

Page 135: ... N 0 III Ql Ql 0 II Ql Ql N N I l 0 11 1 S 11 1 11 1 0 I U Q t II I l 0 0 I I l 8l 8l Ql I l 2 2 s 0 0 N l Il l 0 lQ III U Eo 0 0 III U 0 l E U COM M U N I CAT ION S SYMPTOMS Transmits garbled data X X XX Receives garbled data X X XX Receives garbled data when ter minal should not be receiving X XX No I O with communications sys tem X X XX X MIS C ELL A N E 0 U S S Y M TOM S Intermittent correct o...

Page 136: ...site video at video jack J15 X Terminal inoperp tive raster present X X X X 6 2 5 Removal and Replacement Procedures Cabinet Removal and Replacement To take the top section of the cabinet off remove the five screws three on the front two on the back shown in Figure 6 1 and 6 2 Lift the cabinet straight up To replace the top section of the cabinet lower it straight down over the internal assembly R...

Page 137: ...MAINTENANCE AND REPAIR SECTION 6 Figure 6 1 Cabinet mounting screws front Figure 6 2 Cabinet mounting screws rear 6 14 ...

Page 138: ...g out from both ends NEVER PULL ON THE CABLE OR THE LID OF THE PLUG When picking up a card first place one hand against the surface on which the card rests Then pick the card up with your other hand To put a card down first place the hand not holding the card against the surface on which you want to place the card This precaution discharges body static so that you can safely lay the card down To r...

Page 139: ...y as the socket into which it is being inserted 6 After the card is seated and the connector s plugged in remove the hand holding the CRT face or the terminal chassis Keyboard Removal and Replacement Removal of the keyboard from the terminal is done this way 1 Remove the top section of the cabinet as described earlier From underneath remove the four keyboard mounting screws shown in Figure 6 4 NOT...

Page 140: ...witch proceed as follows 1 Remove the key cap by pulling straight up with a key cap removal tool 2 Remove the keyboard as described earlier 3 Locate the two leads of the defective switch on the back of the circuit card 4 Unsolder both switch leads sucking all solder from the mounting holes 5 Lift the switch straight up if possible 6 If the lead solder connection is too strong try wiggling each of ...

Page 141: ...he post cap counterclockwise and pull straight out Remove the old fuse from the cap To install a fuse insert it in the post cap push it into the post and turn it clockwise to lock it in place Monitor Deflection Board Removal and Replacement The Monitor Deflection Board is located above the neck of the CRT To remove the board disconnect EIOI through EI04 and PI02 through Pl12 excluding PI09 see Fig...

Page 142: ...dures in Paragraph 6 2 This objective is best met by isolating the problem to a component on a circuit card or assembly and replacing it with a good component A secondary objective is safety Thus CRT removal and replacement are recommended bench service procedures 6 3 2 Requi red Equipment and Materials NOTE Equivalent substitutes may be used Oscilloscope Tektronix 465 1ul timeter Triplet t 310 Di...

Page 143: ... terminal power is on Consider temperature possibilities when investigating an intermittent problem Transistor failure is often caused by failure of another component Investigate this possibility before replac ing a transistor Keep terminal clean inside and out Solder qulckly and use heat shunts to prevent heat damage Avoid excessive card extraction and insertion Replaceable Parts Replaceable part...

Page 144: ...t 2 Refresh Buffer Card Slot 3 Timing Control Card Slot 4 Refresh Memory Card Slot 5 Refresh Control Card Slot 6 Processor Card Slot 7 Program Memory Card Slot 8 RS232 Interface Card Modem Slot 9 RS232 Interface Card Storage Slot 10 RS232 Interface Card Printer Slot 11 Terminator Card Slot 12 Regulator Card Slot REG LED Assembly Keyboard Assembly Power Supply Assembly CRT Monitor Assembly Such det...

Page 145: ...ed conductive paths solder bridges broken leads and other abnormal conditions Visible troubles usually have an obvious remedy Dynamic Testing Procedures for isolating problems to the component level in each section of the terminal are given in Paragraph 6 3 7 In many cases malfunctions are related to possible component failure These procedures should always be used with trye information supplied i...

Page 146: ...NAL DO NOT INSERT ANY CARD NOT MEETING THESE REQUlRE mNTS NOTE 1 Waveforms supplied in this paragraph a e consecutively numbered These numbers appear on the waveform photos and in the photo captions Correspondingly numbered call outs on the applicable schematic indicate where the waveform can be observed Waveforms are referenced to chassis ground NOTE 2 Should the insertion of any circuit card loc...

Page 147: ...chronization internal IF SIGNAL IS INCORRECT OR AB SENT CHECK XE6 6 Timing Control Card Refresh Buffer Card WAVEFORM 2 BLANK Oscilloscope Settings Vertical 2 V cm Horizontal 10 usec cm Synchronization internal IF SIGNAL IS INCORREct QR ABSENT CHECJ XE6 6 Timing Control Card Refresh Buffer Card WAVEFORM 3 Clock Timing Oscilloscope Settings Vertical 1 V cm Horizontal 0 1 usec em Synchronization inte...

Page 148: ...Card WAVEFORM 5 Video Oscilloscope Settings Vertical I V cm Horizontal 2 msec cm Synchronization internal IF SIGNAL IS INCORRECI OR ABSENT mECK CR3 XOl 6 XEI 6 XEl B XEl 1I XEI 3 and circuitry related to these components WAVEFORM 6 Video Oscilloscope Settings Vertical I V cm Horizontal 10 usec cm Synchronization internal IF SIGNAL IS INCORRECT OR ABSENT CHECK CR3 XOl 6 XEI 6 XEI S XEI ll XEI 3 and...

Page 149: ...minal WAVEFORM 8 Not applicable to 8025G Terminal WAVEFORM 9 Parallel to serial converter output Oscilloscope Settings Vertical 1 Vlcm Horizontal 2 msec cm Synchronization internal IF SIGNAL IS INCORRECT OR ABSENTI CHECK XA2 XA4 Refresh Buffer Card 6 26 SECTION 6 ...

Page 150: ...T CHECK XA2 XA4 Refresh Buffer Card WAVEFORM 11 Clock Timing Oscilloscope Settings Vertical I V cm Horizontal 0 1 usec cm Synchronization internal tF SIGNAL IS tNEORRECf OR ABSENT CHECK Timing Control Card WAVEFORM 12 Clock Timing Oscilloscope Settings Vertical I V cm Horizontal 0 2 msec cm Synchronization internal IP SIGNAL IS INCORRECf OR ABSENT CHECK Timing Control Card SECTION 6 6 27 ...

Page 151: ...al 0 1 usec cm Synchronization internal IF SIGNAL IS INCORRECT OR ABSENT CHECK Timing Control Card WAVEFORM 14 H8 Clocks Oscilloscope Settings Vertical 0 2 V cm Horizontal 0 1 usee em Synchronization internal IF SIGNAL is INCORRECT O R ABSENT CHECK XES 6 Timing Control Card SECTION 6 6 28 ...

Page 152: ... internal IF SIGNAL IS INCORRECT OR ABSENT OIECK XEl 3 6 8 and 11 XDl 3 6 8 and 11 WAVEFORM 16 Each CG bus line one half page data Oscilloscope Settings Vertical 1 V cm Horizontal O S msec cm Synchronization internal IF SIGNAL IS INCORRECT OR ABSENT CHECK XEl 3 6 8 and 11 XDl 3 6 8 and 11 WAVEFORM 17 Refresh shift register outputs one half page data Oscilloscope Settings Vertical 2 V cm Horizontal...

Page 153: ...EFORM 19 Next line shift re gister inputs one half page data Oscilloscope Settings Vertical 1 V cm Horizontal 2 usec em Synchronization internal IF SIGNAL IS INCORRECT OR ABSENT CHECK XE4 1 4 10 13 XD4 1 4 10 13 XB6 2 XC4 3 6 8 11 XB4 3 6 8 11 XD6 12 Refresh Memory Card WAVEFORM 20 CPU BUSY Oscilloscope Settings Vertical 2 V cm Horizontal 10 usec cm Synchronization internal IF SIGNAL IS INCORRECl ...

Page 154: ...Synchronization internal IF SIGNAL IS INCORRECI OR ABSENT a tECK XC6 6 XCS XDS l1 XDS 3 Timing Control Card WAVEFORM 22 REG 1 CLK Oscilloscope Settings Vertical 2 V cm Horizontal 0 1 msec cm Synchronization internJ1 IF SIGNAL IS INCORRECI OR ABSENT OIECK XBS 8 and related input circuitry SECTION 6 6 31 ...

Page 155: ...ion internal IF SIGNAL IS INCORRECI OR ABSENT CHECK XES 6 XFS 4 XFS IO Processor Card WAVEFORM t4 V SYNC Oscilloscope Settings Verticle IV em Horizontal 10 usee cm Synchcnization internal IF SIGNAL IS INCORRECI OR ABSENT CHECK XF4 12 XE3 circuitry related to pin 4 of XE3 WAVEFORM 25 H SYNC Oscilloscope Settings Vertical 1 V cm Horizontal 0 2 usec cm Synchronization internal IF SIGNAL IS INCORRECI ...

Page 156: ...ECT OR ABSENT OfECK XFI 2 4 6 8 XCI H BLNK circuitry WAVEFORM 27 POLL Oscilloscope Settings Vertical I V cm Horizontal SO usec cm Synchronization internal IF SIGNAL IS INCORRECT OR AB SENT CHECK XD4 6 XE4 WAVEFORM 28 POLL Oscilloscope Settings Vertical 1 V cm Horizontal I usec cm Synchronization internal IF SIGNAL IS INCORRECT OR ABSENT CHECK XD4 6 XE4 SECTION 6 6 33 ...

Page 157: ...BSENT CHECK XBl 8 Q2 QI YI and related com ponents WAVEFORM 30 LDCNT Oscilloscope Settings Vertical 1 V cm Horizontal 10 usec em Synchronization internal IF SIGNAL IS INCORRECT OR ABSENT CHECK XE2 8 XE6 XF6 4 XFS l3 XDS WAVEFORM 31 H320 Oscilloscope Settings Vertical 1 V cm Horizontal 10 usec cm Synchronization internal IF SIGNAL IS INCORRECT OR ABSENT CHECK XC2 SECTION 6 ...

Page 158: ...SENT OIECK XBI 3 XBl ll XAI SECTION 6 Refresh Control Car d Plug the card onto the extender card and insert in the terminal Check for the following signals in the order given WAVEFORM 33 Each RD bus line Oscilloscope Settings Vertical I V cm Horizontal I usec cm Synchronization internal IF SIGNAL IS INCORRECT OR ABSENT CHECK XEI 4 6 8 10 XE2 4 6 8 10 6 35 ...

Page 159: ...d input circuitry WAVEFORM 3S Address COW lter XC4 outputs Oscilloscope Settings Vertical I V cm Horizontal I msec cm Synchronization internal IF SIGNAL IS INCORREcr OR ABSENT CHECK XC4 XC3 XA3 11 XB4 3 XB4 6 XB6 8 XD4 2 XD3 2 XE2 l2 Timing Control Card WAVEFORM 36 RM 4 S 6 7 Oscilloscope Settings Vertical I V cm Horizontal I usec cm Synchronization internal IF SIGNAL IS INCORREcr OR ABSENT CHECK ...

Page 160: ...CHECK XCS WAVEFORM 38 RMO l 2 3 Oscilloscope Settings Vertical 1 V crn Horizontal 2 usee ern Synchronization internal IF SIGNAL IS IN ORRECT OR ABSENT CHECK Input circuitry to XCS Refresh Memory Card WAVEFORM 39 Address counter XC3 outputs Oscilloscope Settings Vertical 1 V crn Horizontal 2 usee em Synchronization internal IF SIGNAL IS INCORRECT OR ABSENT CHECK XC3 SECTION 6 6 37 ...

Page 161: ...Memory Card WAVEFORM 41 MA bus enable Oscilloscope Settings Vertical 1 V cm Horizontal 1 usec cm Synchronization internal IF SIGNAL IS INCORRECT OR ABSENT CHECK XB4 3 XB4 6 related input circuitry WAVEFORM 42 RM 4 5 6 7 Oscilloscope Settings Vertical 1 V cm Horizontal 2 usee em Synchronization internal IF SIGNAL IS INCORRECT OR ABSENT CHECK Refresh Memory Card SECTION 6 6 38 ...

Page 162: ... CHECK XC6 2 XC2 Timing Control Card WAVEFORM 44 CPU Timing Oscilloscope Settings Vertical lV em Horizontal 2 usec cm Synchroni tion internal IF SIGNAL IS INCORRECT OR ABSENT CHECK XA4 XB2 circuitry related to inputs to XA4 WAVEFORM 45 Each MA bus line Oscilloscope Settings Vertical 1 V cm Horizontal I usec cm Synchronization internal IF SIGNAL IS INCORRECT OR ABSENT OIECK XF6 8 XE4 3 6 8 ll XF4 3...

Page 163: ...11 related input circuitry WAVEFORM 47 CPU BUSY Oscilloscope Settings Vertical I V cm Horizontal 2 usec cm Synchronization internal IF SIGNAL I S INCORRECT OR ABSENT CHECK XE6 8 and related input circuits WAVEFORM 48 T2 Oscilloscope Settings Vertical I V cm Horizontal 2 usec em Synchronization internal IF SIGNAL IS INCORRECT OR ABSENT CHECK XB4 6 XA2 3 input circuitry re lated to XA2 3 SECTION 6 6...

Page 164: ...ical 1 V cm Horizontal 2 usee em Synchronization internal IF SIGNAL IS INCORREef OR ABSENT CHECK XE5 ll XAS WAVEFORM 50 SYNC Oscilloscope Settings Vertical 1 V cm Horizontal 0 5 usec cm Synchronization internal IF SIGNAL IS INtORREef OR ABSENT CHECK XC2 SECTION 6 6 41 ...

Page 165: ...nternal IF SIGNAL IS INCORRECT OR ABSENT mECK XEl 3 6 8 11 XGl 3 6 11 related input circuitry to XEl and XG1 Timing Control Card WAVEFORM 52 POLL om Oscilloscope Settings Vertical 1 V cm Horizontal SO msec cm Synchronization internal IF SIGNAL IS INCORRECT OR ABSENT CHECK XG6 3 and related input circuit ry Timing Control Card WAVEFORM 53 Reset Command MAl 2 3 4 Oscilloscope Settings Vertical lV em...

Page 166: ...ng Control Card WAVEFORM 55 RS CLK Oscilloscope Settings Vertical 1 V cm Horizontal 1 usec em Synchronization internal IF SIGNAL IS INCORRECT OR AB5 NT mECK XBl 2 Timing Control Card WAVEFORM 56 Address comparator output Oscilloscope Settings Vertical 0 2 V cm Horizontal SO msec cm Synchronization internal IF SIGNAL IS INCORRECT OR ABSENT CHECK XD3 3 4 10 11 SECTION 6 6 43 ...

Page 167: ...Synchonization internal IF SIGNAL IS INCORRECT OR ABSENT QIECK XD3 2 Keyboard Card encoder WAVEFORM 58 DSO Oscilloscope Settings Vertical 1 V cm Horizontal 2 msec cm Synchronization int rnal IF SIGNAL IS INCORREt1 OR ABSENT OIECK XD3 2 Keyboard Card encoder WAVEFORM 59 KYBD STROBE Oscilloscope Settings Vertical 1 V cm Horizontal 0 1 usec cm Synchronization internal IF SIGNAL IS INCORREt1 OR ABSENT...

Page 168: ...O ll XES 3 4 10 ll input circuitry to XCS XDS and XES WAVEFORM 61 H40 CP Clock Oscilloscope Settings Vertical 1 V cm Horizontal 20 usec cm Synch onization internal IF SIGNAL IS INCORRECT OR ABSE T CHECK XD3 4 Timing Control Card WAVEFORM 62 Click Oscilloscope Settings Vertical 2 V cm Horizontal 10 msec cm Synchronization internal IF SIGNAL IS INCORRECT OR ABSENT CHECK XAl SECTION 6 6 45 ...

Page 169: ...AI WAVEFORM 64 Beep Oscilloscope Settings Vertical 1 V crn Horizontal 0 1 msec cm Synchronization internal IF SIGNAL IS INCORRECT OR ABSENT CHECK XA4 l0 Ql XAl Refresh Buffer Card WAVEFORM 65 Beep Oscilloscope Settings Vertical 5 V cm Horizontal 10 msec cm Synchronization internal IF SIGNAL IS INCORRECT OR ABSENT CHECK XA4 l0 Ql XAl Refresh Buffer Card SECTION 6 6 46 ...

Page 170: ...er supply and regula tor circuitry is used in the terminal Use standard voltage and resistance measure ment techniques to isolate problems in these two sections Terminator Card The Terminator Card consists of five integrated circuit resistive networks Xl through XS A malfunction in a network is detected by mea suring the res stance between pin 16 and each of the other pins 1 through 15 The reading...

Page 171: ...sh ground connection f If the regulator continues to perform abnormally the problem is probably a shorted electrolytic capacitor or defective com ponents in the regulator circuit g If the regulator performs normally isolate the problem to indivi dual stages as outlined in Step 3 3 Check for the following waveforms in the order given WAVEFORM 66 Q10l Anode Oscilloscope Settings Vertical 1 V cm Hori...

Page 172: ...22 Collector OScilloscope Settings Vertical 50 V cm Horizontal field rate Synchronization external with leading edge of V SYNC IF SIGNAL IS INCORRECT OR ABSENT OIECK CRl03 RI13 and CI07 RI2l WAVEFORM 70 Ql09 Collector Oscilloscope Settings Vertical 5 V cm Horizontal line rate Synchronization external with leading edge of H SYNC IF SIGNAL IS INCORRECT OR ABSENT CHECK R142 and Cl16 Cl14 QllO Q109 an...

Page 173: ...ORM 72 Ql14 Collector Oscilloscope Settings Vertical 0 5 V cm Horizontal line rate Synchronization external with leading edge of H SYNC IF SIGNAL IS INCORRECT OR ABSENT CHECK C121 R153 R156 and R157 C122 CRl09 R152 C122 Qll4 and Ql15 WAVEFORM 73 Ql15 Collector Oscilloscope Settings Vertical SO V cm Horizontal line rate Synchronization external with leading edge of H SYNC IF SIGNAL IS INCORRECT OR ...

Page 174: ...FORM 7S Radiated Pulse from Tl03 10 1 probe held 2 away AC coupled Oscilloscope Settings Vertical 50 V cm Horizontal line rate Synchronization external with leading e ge of H SYNC IF SIGNAL IS INCORRECT OR ABSENT OIECK CRl16 and C127 Ll24 Tl03 WAVEFORM 76 CRllS Cathode Oscilloscope Settings Vertical 50 V cm Horizontal line rate Synchronization external with leading edge of H SYNC IF SIGNAL IS INCO...

Page 175: ...s proceed as follows 1 Scrape away any coating from the card pads with a sharp edged instru ment 2 Use a heat sink shunt to protect adjacent components 3 With a contrOlled heat solderl ng iron remove component and clear excess solder from mounting holes as quickly as possible 4 Bend replacement component leads to fit the distance between mounting holes and insert leads 5 Use a heat sink to protect...

Page 176: ...lacement To remove and install the CRT proceed as follows 1 Turn the terminal off and remove the ac plug 2 Wait 2 to 3 minutes for the high voltage H V supply to drain 3 Remove the top section of the cabinet refer to Paragraph 6 2 5 4 Peel the H V cap on the red lead back from the CRT see Figure 6 6 5 Discharge H V by shorting the H V lead and CRT anode button to ground Also short the anode button...

Page 177: ...OU MAY GENTLY SUPPORT THE NECK BUT ONLY TO STEADY AND GUIDE THE CRT 12 Place the CRT face down on a soft grit free surface 13 Loosen the yoke mounting screw refer to Figure 7 14 in Section 7 and pull the yoke straight up and off the CRT neck WARNING NEVER PRY THE YOKE OFF THE CRT NECK TO DO SO MAY SCRATCH OR BREAK THE CRT 14 To replace the CRT install the deflection yoke and repeat steps 1 through...

Page 178: ...tor Card see Figure 7 1 This card is installed in the first card cage slot left side as viewed from the rear of the terminal Connect the positive and negative leads of the multimeter to test points TP 5 REG and TP GND respectively Set R4 to provide 5 00 0 10 V dc if required TP 5V REG Figure 7 1 Regulator Card 5 V dc adjustn nt and test point locations 7 3 CLICK BEEP VOLUME The click beep volume a...

Page 179: ...REA Preliminary Procedure Turn the terminal on and enter characters from the keyboard to fill the screen completely The pattern shown in Figure 7 3 gives a good picture for making CRT display adjustments With an oscilloscope check that horizontal and vertical sync signals are a nominal 4 volts peak to peak Horizontal sync is available at pin 6 and verti cal sync at pin 9 of Pl12 the plug connected...

Page 180: ...set too high 7 4 2 55 V de B Adjust The B adjustment R134 is located on the Monitor Deflection Board see Figure 7 4 Connect the positive lead of the multimeter to the cathode of CRl06 and the negative lead to the anode of VRlOl see Figure 7 4 Set R134 to provide 55 volts de 7 4 3 Video Gain The video gain adjustment Rl19 is located on the Monitor Deflection Board see Figure 7 4 Adjust Rl19 see Fig...

Page 181: ...ADJUSTMENTS HORIZONTAL WIDTH HORIZONTAL CENTERING FOCUS GROUND Figure 7 4 Monitor Deflection Card CRT adjustment and test point locations 7 4 SECTION B ADJUST 55Vdc VERTICAL HEIGHT ...

Page 182: ... a guide S Short the input end of RIOI to ground and set R103 vertical hold until the video presentation rolls down slowly 6 Remove the short used in Step 4 7 Recheck height and vertical linearity Horizontal Adjustments Except for the horizontal linearity adjustment l all horizontal adjustments are located on the Monitor Deflection Board see Figure 7 4 You will find the horizontal linearity adjust...

Page 183: ...ADJUSTMENTS Figure 7 5 Vertical linearLty adjustment R109 incorrectly set 24 line display shown 7 6 SECTIO ...

Page 184: ...ADJUST 1ENTS SEen 0 7 Figure 7 6 Height adjustment RI07 incor rectly set 24 line display shown 7 7 ...

Page 185: ...AD J usn IENTS Figure 7 7 vertical hold adjustment R103 incorrectly set 24 line display shown SECTlO 7 ...

Page 186: ... n t I 1 II I lh III H H f t t t t IH f I u t t t f 1 t t t H t tIf t t t IlI 1 I I IIII 111 1 III II 1 1 1111 t t t t t l 11 111 I I I t l 1 1 f t 1ft t tttttt tittil j t t J l I t I t II II 4 f t H t l l i tt t I t t lttt t c t t t t I n t It I it l ti lt t Of 1t N t l in tt f fo t I PH t tHn H H t 1 1 l ttlIH t i i f I f f 4 t It lit H1 14 Ii IfI t t It t If t it t t i t t r Figure 7 8 Vertical...

Page 187: ...ADJUSTMENTS Figure 7 9 Horizontal width adjustment L104 incorrectly set Bri ghtness control too hi gh 24 line display shown 7 10 SECTION 7 ...

Page 188: ...ADJUSTMENTS Figure 7 10 Severe misadjustment of hori z ontal centering adjustment R143 Note foldover on right side 24 line display shown 7 11 SECTION 7 ...

Page 189: ...the BRIGHTNESS control up until the raster is visible see Figure 7 13 7 If the video is not centered horizontally within the raster center the video with R143 horizontal centering 8 If the raster is not centered horizontally refer to paragraph 7 4 6 Centering Adjustments j Two ring magnets mounted on the neck of the CRT see Figure 7 14 position the raster on the CRT face Rotate the centering magne...

Page 190: ...6J JUSTMENTS Figure 7 11 Horizontal linearity is positioned on neck of CRT for best overall linearity from left to right 7 13 SECTION 7 ...

Page 191: ... 7 12 Example of a horizontal centering problem caused by incorrect setting of the horizontal centering adjustment R143 or of the raster centering magnet dis cussed in paragraph 7 4 6 24 line display shown 7 14 SECTION 7 ...

Page 192: ...y set turn the control up until the raster is visible The photo illustrates the correct setting of the horizontal video centering adjustment Rl43 and the raster centering magnets Note that the vertical linearity adjustment RI09 is incorrect ly set 24 line display shown SECTION 7 ...

Page 193: ...ADJUSTMENTS Figure 7 14 Raster centering magnets are used to center the raster vertically and horizontally on the CRT screen The deflection yoke is used to correct raster tilt 7 16 SECTION 7 ...

Page 194: ...sr cnON 7 rigure 7 15 Deflection yoke incorrectlY set 24 line display shown ...

Page 195: ...DRAWINGS S I _ _ _ _ _ 1_ 5P ___ _I _ _ S Q _ _ _ _ s L ____________ _______________ NOT1 U L6 5 OT RWtSS SP C F If C Jc e G I I L Ow TO BE 4 0 VIA Y i T r MAl CO PO VT T s L r J ...

Page 196: ...__ 1 Too C l CS CH I 0 GN O ____ _ _ lI L O_O_Y__ v ______ G NO 0 en CONI lt caNe iI r i f l 2r TIi ooe or tPI c Tltt f S i T Iioo t T TP1o o r 1 ___ _ _ Q 4 __ 5 q _ COM _ _ _ 4 i SEcrIO 8 8 1 lIR 6 m AllC T lAG RCMRor ...

Page 197: ...DRAWINGS DDDCDDDD DDDCDDDD DDDDDODC ODDD 0 ODDODD DDDDD DDDDDC DDD 0 0 0 DDo B DOD DOD DOD DOD DOD ODD DD T1TLI PWB l E t eOARt E aY ...

Page 198: ... 5 MO 1 0 xe x3 aOI 7404 J71 r P P R 8 1 C MioWT CON Y I 12V i _ _ 10 3CW I oRT 0 5 c c w I 1 1 AC III IKPU 2 I HI OUTPuT rhr 4I 5 EARTII 6NO I I NOTES Uttl t anua WISE 5PECI IEO I L 1I 151STOII I w 5 2 t I L DIODE AU 11 4914 3 0 01 VIi IOW 5 OWW O H 02 VER510w OMIT SWITClo El 58 l M1Lu AMO DIODE CII 30 TI4 ellS CII 40 eIL41 c IL C t60 CIl Z CII A II VI TIOI6 1 01 T O RO SL SHIFT LOCI I O Oli OUTP...

Page 199: ... I I I i J REG JI J2 J 4 J j 7 IJOTE5 ul lu O J OE 5Pf c lrIF JQ I4 Ct PLU SlOE 0 OO 01 A6 SIoIC WN OM r CQ N_ INOtCA O ON DA6 l 0 2 Ie I26tON 0rI1 1Il 01 A NN o li C C CIO CII ON QM o I en Ve loN ONI Y TITU PWB NSSY aoARO ...

Page 200: ...o 3 o BDe 7 0 0 r r C 0 C 23 r r 0 0 ce6 0 0 0 4 0 T 0 0 o o 0 0 0 DB ____ __ 0 2 0 t C 0 0 _ ______ 27 e 0 0 082 i o 0 c o R T 0 0 3 1 0 0 eB 0 c 0 3C 0 0 l 0 C 3 CI o_ 0 ve 4 0 0 0 l r v c r o ___n 0 0 O __o 0 G DB O 0 0 J v _0 C 0 O 0 0 0 DB C 0 0 0 0 0 0 O 7 0 0 0 0 e 7 III 0 N 0 o r O o o o C 4 C 0 0 0 0 0 _o o 0 0 I Q O 0 04 O TOO D 0 0 0 ____ 4 0 0 0 2 j O O O O 44 0 0 GATE 0 0 0 0 0 0 I I ...

Page 201: ... l l t l W 0 l r NA 1 t 1IAI I I willi IIl0M 1llUD6i OWN TO TI TERM I Willi FROM IllUDGtI AIo NOWN TO TI TlRN w I J t T WIR WITW Toe u III utol ITEM INT TOOTW I Q IC WIIIN NOT IU IOUIO WITH TIM12 I CONFIGURATION A CONFIGURATION BON FOLLOWING PAGEl P I PI ROX 4 ONLY _ I rr III 1 l Il J i I RE L ______ I l APPROx OTHER CoAPI L 4 l o C OMPONENT l A OUTLINE 8 11 elt ft EfCtWJGGt 8LE Wf I14 07 04 1 1 ...

Page 202: ...0 C OWPON NTlI I I WI IoIOT TO UUlI IN A r t1 oU Ll WITH THE UIUotIN l l L l el TWUN TH LOUI WAIHI WITt Tou UP_ 00 II nEN 4 WHE NOT IUI PUaO WITH 1 ITI _ BLU CONFIGURATION B E ttl ZEA JtP ACn O TAIL A OUAIL Ii t I NOt i acALI NOf II REF 75 APPROK 4 CN Y t 1 1NTl RC 5l WrrM 01 01ti 01 5 W6 SC MM1C TlTLI POWG R SUPPA ASsQl 6L c ...

Page 203: ... e z I I 2 2 3 6 7 I 0 4 4 I I S 5 iI iI r fij f AT SINKASSY 107 042 01 I QI I V I I I I I I I I _ 1 I I e 0 g III 0 r 2 5 8 JP63 I I 2 5 7 I 9 jJ63 GIlN 11i GIlN 6 YEL 6 GIlN 16 yEL It 8LU 20 yEL 20 BLII 1 BI It 11i 8LK 20 NOTE 1 1110 20 ILK ZO IIfD lO 111 1 20 I _ 1011 DC TO MONITOR II LATOI 2 Z IOV DC AETlJliIIl TO NITOR CIIA s s J61 PSI I MOTHE 99 41 RBOARD 4 01 REG I H I 11 10 I tt I _ 1 I I ...

Page 204: ...eN f N S ID I 7 N I 4 8N s N S NOTES tJNlPS S onttRW S1 SA CIFlep III 11 00 2 0 A W eW WtR E 11 E M 4 4 BE TWEEN e t E 2 I CI IS Al LOWEO TO 13 400 MAX HEIGHT 7 N 5 C5 7400N I ll C 740CotN I7 N S IeA S k I fl o N si tB4 7 OON I ltA 4 74tO 7N 5 B ...

Page 205: ... _ I I _ c L _t _ I_ I_ I J ro _ l 1 I J I b l2 __ 1 T 4 I 4D 49 1 D Y 41O f P t I I r roc 10 po 4 i WF48m 0 5 _ m t F Af la_ O_IO YL J e l I u I W 47 IID S Y y Lf k I I _ _ I __ r __ c K I E Ii J _ L f l 1d 9 4 e 4 J n l I tl 41 Lon 1 WFISO WF 1 b o L a c r oL y I r 49 l 7 H 1f Aq Li r __7 _ r iJ c e le L r _ I 4 T o L 4 4 WFa I 1 L ________ ______ __ ___ _____ __ __ Lfi_ fi l oJ 1 4 iN L_I ___ j...

Page 206: ... 16 2 15 3 14 OPTION OPEN JMPR OPEN JMPR OPEN OPEN OPEN JMPR JMPR i if5t l 4 1 e 7 JJ OJ J j I 3 s 0 I 2 19 910111213141516 1 J lSI ADDRESS JUMPER DETAIL 2 S 18 SEE ADDRESS TABLE I 1 JI N01l S W s flIeR1UI sPeClP EP J M4 7 10 5 Il I flE Pd vq S 1J iE R OF omON ISAU Ovaro 10 00 MAY r J 4 13 OCTAL ADDRESS LOCATION JMPR 0000 7777 JMPR 10000 17777 OPEN 20000 27777 Pftl o f c N 7144 1 8S 1 1 l 1 J to t...

Page 207: ...H 1 t i H _r mr r F p t r t t H H H H j P Hf t1 t j P p 01 5 AI JCf aca Jl c H AI C A AU I ill 7 7 t fI c P t vee r rlTrH J po R flOfNC T 1 0 c cA l A c o Ie F t DES C J HATlOMS C I I 1 4 I t i H t 1 t t t A 11 1 1 H r R SBCTION 8 2 6 X f 1 1 S w it C I 51 J 6 V 71 1 A e 7 v 7 8 17 ...

Page 208: ... 101 1 oZ4 o4 o o 2102 2 XOI XO xcI C e XDI XDc LOAO o o JUMPEIlS 0 1 7 HOO 74 3_ Go xet xr t 1 p 14 Z 7 10 XEZ XI Z 1 1 14 I I 7 10 oTes UtJ O l H eJI J e SPeCIFIeD OJ Re f2 SH RAM BuFFeJ2 E O JUMPlO R5 ON VV NOTES OPEN JUMPER A B J A OJ ...

Page 209: ... 0 1 a 4 iii iii AU 0 Ilr I a 1 K i AU 4 iW XA I f P xes I rn I L J xes f f r U XO 5 I t f 11 IN l t GHO I 5 SECTION 8 OO 4 IF 2 IIXfZ r r rr r J U X 6 I lAl ffi f ffi fa f I L L I r r i 166 I xee I 81 l m ffi I L L 0 J W f 1t J f xC xce I f rn f tl1 f f L L L r u r U XD6 I X07 I IJ 06 U f 00 l t t I L an 8 19 T TScH6fllAl1c DIAGAAM a l et RAM IIWGNOqb _ l r vS ...

Page 210: ...l D4 5 C4 S 7 0 740 2 74 e I E 5 to 5 C S 7404 7400 7474 c I c 040 S I eGo 5 74 0 7427 4H06 _ ill C 1I LoweD TO 4 0 AX H I T K 1 Q I 51 5 It 74Oc 4 S S S 7417 744 11 I S I u 3 5 7417 741c 1 A c r S4 5 A 4 5 74 e 7436 c c s B 5 I 5 7400 7410 S 9I I 8 5 I 1 404 74 07 I _ _ I I co 6 TlTU PW8 ASS LY ReFRE SH OFFER ...

Page 211: ... l f F 1c I ilII5J rC oil II ____ A_ ii Il 0144 p T____T J 4llClo e v Il or 1 74 S 17 7404 RUERENC 4 CE C O o LA u o 0 J IJo4 ac oc u P JI CJ lt I l14 RtF OE G J Nil o v a vu NO o 0 2 764 e 41w 10 e 4 114 4 t 4 7 4tO 7 t 741 C r 1 eo 0 7400 7 e ltl 740 1 4 7 7 I 0 1 1 74C6 14 7 CO 1 1 I DI U OO II 0 74t 7 4 X ac _ L g L r 1 t D I I IZ RT Y 4 O O O I I 1 4 t 31 4 RII _t ti ii g 7 II4c _ I r1 t __ o...

Page 212: ...DRAWINGS ceJ XC 14 00N 1 1 I t NofE LJNl oS O ee v Jt e 5PCClj Je O mMAJ CoMPoNEI Jr 5I4AL L e 376 Ex pr C7 Be A oweo A MAl r i SI i r Of 4 10 I fIlLI PWB g 6LV R fRa CCAAP OL ...

Page 213: ... XC4 c s c 741 J I 741 ltDt j AE4 XE E 14 b X 1Z D _ o a aq l el I t 14 14 CC 14 14 14 Ie 14 I 14 I J i j 14 p 7 e 7 8 7 7 7 PIott T INO U P il I__ fJ 5 I r r UK CIIUIl 5 E C 74C XD P s Z 74C4 OS P I OZ 1oUl4 xO ot P l I c ACE v rr c r Al e I 5 2 04 6 we iA AI MAw A7 A 1 1AIQ All MAIS ...

Page 214: ...DRAWINGS 0 0 0 0 Q G n l ac eescp c III to III Nm S UHI E S SE PECIFiEl mIJ I I CO Pol lO Bt 1 Nee P IoI IOAJi t rreM 7 O BeTWeeN FreM7 A O 21 l f loS o o li4 ...

Page 215: ... 780 CP 3 n3 CW IK t R4 100 I z 2 2 7906 CP CRI IN52 338 IUF I S 781 c p 3 C l It I to G LO 0 1 Mc R ef BOARC r Q B ftil 64 1 o Isl TP Nt 1 GI ID CIO 10 ISVDC 7 O 12VOC c CII 1 livoc TP RE G Oii U LE SSa OiHl RW Cit S C l t t AL tt TOlt A t 4W 6 CAIt60N 2 ALL RE 5I TOR 5 I V ES ARE I OHM S S ALL CAPAC ITOR VAlUES MICJOFARADS 0R4 TO BE ADJUSTED TO PROV OE 5 15 t 0 10 vee T THE R 6 SV 1 EST POINT LO...

Page 216: ...DRAWINGS xu 74 7 xU T 102A XG4 7407 l lIU 7403 b Cb I ...

Page 217: ...I 6ri1 i 411 l t J III 4 a1 0 0 o A ooc It B rl WJ c 4 Q t _ E W r loU L 1 I lL1 1 t i I 1 1 1 tI j t I A 1 i u I iIoNi M j 4100 r _0 l O u WP L I T A Co J1 I I l A 1 T I o 10 J a t t i 1 1 I I I I I I I A r l l 11 t n L 00 1 h lJ 1R U 1 _ ar r w TICO I_ o LUtO 1 4 4 SECTION 8 JU 1 uQ 2 UItS3Z woo O tl t l 000 0 41 J Sl At S l 6 t t 4 G 110 Ie 00 c _ 1 Clt 1 I It o M b o l I 1 1 27 ...

Page 218: ...DRAWINGS XAI G C 3 Z q c IXA 3 9 C5 IXA4 0 11 9 C6 I AS 1 L TITLE PWB ASSEM SlY 1 eRMltJlrnlR ...

Page 219: ... 47anJ iiiT 3 EXTWRT 25 S REAIW 15 6 1 P o c t 16 15 t t 1 1 1 10 6 IS I 11 11 It 10 1lC 5 I It 10 tEt It 1 4 11 11 l 10 115 to 11 11 10 3 1 T S l IC 21 RE S 1 NC 21 R CLK 20 Boe6 Ie 8085 SPARE 17 lOB 3S PR 7 PR E N s READ GA 1 e 3 AD65 31 ADSL l 4l roo I SPA RE 5 3 HDRIVE 10 M IS I III TR RQ II Ie tL MA 51 SPA RE 1 4 PCi 68 MAI t EoE 1A b t MA 2 POU i t 61 MAli POI L 714 t MAt 0 MA IO IY 1 v eo G...

Page 220: ...0 14114 r104 S 1 4 A 4 S 5 C4 l41C1l S 1 5 lIj to S lK S I lCD t S c e S 14L O 141 0 l U1 S t 4 to S I lIC S 74D4 A 7 ct 1410100 Norf UNI _e SPioC C EQ MA COMFO e r e tIl114r 1 C Is Au oweo To 8 400 M l l 9Io1r B I lm t i e I I hd S C 144D J AJ c a at I 741i 1 TITLI e ASS eLY llM NC r c otJlROL i 4 I 62 o1 rovCo ...

Page 221: ...ilO 4Q 10 a C 4 14101 1 14 I 14 IH O 41100 Ib Ct Ol U AI5T 41101 8 110 1I r 4 8 ai 4 100 14 74 14 14 C 414 1 14 40e 1 14 4LOl 14 441 8 404 UNO 6LNI 30 RI 10 2 71 Z1 TE T A RI4 ta 2 7K q TE l I RI o C 2 71 I TE c RI to 2 7K Ti5T 0 6 POsi i Mi 3 RI7 H 2 7K TE oT e Ria L 7K NOTe UNL ESS OTIolERwl E SOECIFIEO I ALL RE I rOR ARE 1 4 vy H TE oTY 2 SEE PARn LIST 01 1 CAPAC ITOR VOL1A E TOLE RANCe _ SPARE...

Page 222: ...U OWD 10 K 0 OM t HUN 5 C tlJAII t 7 It IJ N 41 l Lf VPPti R CA l L CN i NU lL of I9H C I I C r f V 1 t W A C fsii C rv I c 41 d 1V 72 1 r S PIt J S IJ I I M CII2 r 1 1 D 1f t K fA IV cl e r rIIrNT7 f 24 J u f f AS V OliO CON IltOL ...

Page 223: ... 1 t c oi 1 CCw 10 l tRT M E O 0 40 4 Rle 210 11 C R3 INql4 It TP I 0 C IW oc t TION CA 0 c ND TP 1 a T TP4 c A A OI Y Tl S Oi 0 c e D ll llII I J I CH CO J 04 f L1 1l 4 In II 0 1lA R I 140 lN 14 C 140 2N o C 740 7 iO j420 a 21 I 7 i i 46tJ 74 1 I II l llCl 4_OC e HEFER 70 APP ICA I qQ 2a FOR C ARAC1 ER E tRA10 ser 1 b ALl Re SI rOR ARE II IV Y 1 AU CAPACITOR VA UE IN MF 1 5 GATE 1 Eh 6 IO 1417 it...

Page 224: ...ant 80 310 41 C26 27 10OF 25V Elect 80 305 29 C24 39OF 10V rant 80 302 08 C13 15 25 10OF 25V 10 Elect 80 305 21 C6 C1 150UF 15V Tant 80 311 58 DIODES CRl 5 7 11 IN914 IN4148 80 404 03 VRI Zener IN5227A 80 404 11 INTEGRATED CIRCUITS XC1 XC2 XB2 7400N 80 460 22 XB3 XB4 XBS 7403N 80 460 59 XD3 7404N 80 460 18 XB1 7408N 80 460 50 XE2 XD2 XC3 7474N 80 460 34 XE6 7493N 80 460 39 XE1 XD1 XA1 74123N 80 46...

Page 225: ...B 13 16 21 24 2 2KO 1 4W 5 80 212 22 Rl 27 28 30 2 7Kn 1 4W 5 80 212 72 R31 32 12KO 1 4W 5 80 211 23 R9 10 22 10Kfl 1 4W 5 80 211 03 Rl1 14 17 15Kfl 1 4W 5 80 211 53 Rl8 20 23 22Kfl 1 4W 5 80 212 23 R3 4 29 39Kfl 1 4W 5 80 213 93 R25 ADJ lOK Cermet Trimpot 80 270 52 XB6 Pack 4 7K 1 4W 5 80 290 50 J23 Socket 16 Pin Dip 80 676 04 TRANSISTORS 22 3 4 5 2N4401 80 419 01 Q1 2N4403 80 423 02 Ejector 40 1...

Page 226: ...CAPACITORS lO F 25V Electrolytic 01UF 100V Disc 1000PF 1KV Disc Diod IN914 IN4148 INTEGRATED CIRCUITS MM5740 BEE N SN7404N INTEGRATED CIRCUIT SOCKETS 16 Pin Dip 40 Pin Dip Resistor 4700 1 4W 5 Carbo Compo SWITCHES Space Form A Single Form A Shift Lock SECTION 9 Assembly 99 453 XXA I OMRON PIN 80 305 21 80 320 93 80 319 05 80 404 03 80 460 95 80 460 18 80 676 04 80 675 10 80 214 71 80 932 10 80 932...

Page 227: ... REF DES IDESCRIPTION I OMRDN PiN CRl CR2 CR5 CR8 L E D Fairchild FLV 104 80 400 01 MOTHER BOARD ASSEMBLY 99 4l4 XXB REF DES IDESCRIPTION I OMRDN PIN CAPACITORS C1 220UF 10WV Tant 80 310 51 C2 Cl1 22UF lSWV Tant 80 311 53 REG J1 J4 PWB Connector 80 Pin 80 612 12 9 4 ...

Page 228: ...307 13 CR1 CR2 RECTIFIER ASSEMBLY 07 046 01 TRANSFORMERS T1 Transformer 85 023 01 T2 Transformer 85 021 01 POWER SUPPLY ASSEMBLY ASSEMBLY 07 041 02A IDESCRIPTION REF DES OMRON PIN CAPACITORS C1 40 000 lJ F 20WVDC 80 305 23 C2 C3 3 900 IF 35WVDC 80 300 67 C4 1 700 lJ F 100WVDC 80 307 13 TRANSFORMERS T1 Transformer 85 023 01 T2 Transformer 85 021 01 CRl CR2 Rectifier Center Tapped Bridge 80 412 11 8...

Page 229: ... 10V Tant Diodes IN914 IN4148 INTEGRATED CIRCUITS 7400N 7403N 7404N 7406N 7410N 7438N 7440N 74L42N 7474N 7475N 74107N 8008 8T380 RESISTORS 2700 S 1 4W 1K 5 1 4W 2 7K S 1 4W 10K 5 1 4W Transistor 2N4403 I C Socket 18 Pin Dip Ejector 9 6 SECTION 9 ASSEMBLY 99 369 01C I OMRON PIN 80 305 21 80 320 90 80 320 93 80 311 58 80 404 03 80 460 22 80 460 59 80 460 18 80 460 73 80 460 19 80 461 22 80 460 42 80...

Page 230: ...ITORS Cl l50UF 10V Tant 80 311 058 C2 thru C14 01U 100V Cer Disc 80 320 093 INTEGRATED CIRCUITS XF5 7404 80 460 018 XE3 XF4 7407 80 461 036 XE6 7430 80 460 045 XE4 XE5 7442 80 460 031 XF3 Resistor Pak 2 2K 80 290 051 XA1 thru XAB Socket 16 Pin Dip 80 676 04 XB1 thru XB8 XC1 thru XC8 XD1 thru XDB XF6 ...

Page 231: ...1777 825126 22 011 65 XD4 H1400 1777 825126 22 011 66 XB5 L2000 2377 825126 22 011 67 XDS H2000 2377 825126 22 011 68 XB6 L2400 2777 825126 22 011 69 XD6 H2400 2777 825126 22 011 70 XB7 L3000 3377 825126 22 011 71 XD7 H3000 3317 825126 22 011 72 XB8 L3400 3777 825126 22 011 73 XD8 H3400 3777 825126 22 011 74 XF5 7404 80 460 018 XE3 XF4 7407 80 461 036 XE6 7430 80 460 045 XE4 XES 7442 80 460 031 Bu...

Page 232: ...t 01UF 10OV Cer Disc INTEGRATED CIRCUITS 2102 2 74HOO 7438 7442 7404 7420 7407 EJECTORS Ejector Ejector Buffered Ram Sub Assembly Resistor Pak 2 2K Resistor 4 7K 1 4W 5 Socket 16 Pin Dip I C Socket 14 Pin Dip Socket Adapter 9 9 SECTION 9 ASSEMBLY 99 44S XXB OMRON pIN 80 311 058 80 320 093 80 460 91 80 460 35 80 461 22 80 460 031 80 460 018 80 460 017 80 461 036 40 109 05 40 109 09 99 433 01 80 290...

Page 233: ...6 IDESCRIPTION CAPACITORS 150UF lOV TANT 01UF 100V Cer Disc INTEGRATED CIRCUITS 7442 7404 7420 7407 I C Socket 14 Pin Dip Resistor 4 7K 1 4W 5 Resistor Pak 2 2K Socket 16 Pin Dip Socket Adaptor 9 10 SECTION 9 ASSEMBLY 99 433 XXC I OMRON PIN 80 311 058 80 320 093 80 460 031 80 460 018 80 460 017 80 461 036 80 675 007 80 214 72 80 290 051 80 675 008 80 625 03 ...

Page 234: ...N 80 461 22 XD6 7427N 80 460 61 XD2 XD3 XE2 XE3 2532B 80 461 34 XE6 7430N 80 460 45 XB5 XDS 7400N 80 460 22 XD4 XE4 7402N 80 460 62 XAS 7410N 80 460 19 XC5 7474N 80 460 34 XA6 74107N 80 460 46 XB2 XB3 XC 2 XC3 74175N 80 460 64 XA2 7442N 80 460 31 XA3 74161N 80 460 58 XB1 XC1 7406N 80 460 73 XC6 XD1 XE1 7408N 80 460 50 XC6 74H08 80 461 49 RESISTORS Rl Rl2 lOon 1 4W 5 80 211 01 Rl3 14 1S 16 1K 1 4W ...

Page 235: ...RS OlUF 10OV Cere Disc 10OF 25V 10 Elec 150MF 15V Tant INTEGRATED CIRCUITS 7400N 7404N 7408N 7420N 7427N 7430N 7438N 74107N 74161N 74163N 7414N Card Ejector Resistor lK 5 1 4W 9 12 SECTION 9 ASSEMBLY 99 457 018 I OMRON PIN 80 320 93 80 305 21 80 311 55 80 460 22 80 460 18 80 460 50 80 460 17 80 460 61 80 460 45 80 461 22 80 460 46 80 460 58 80 460 79 80 461 45 40 109 06 80 211 02 ...

Page 236: ... 15 VDC Tant 0 lUF 20 Cere Disc RESISTORS Fixed WW 20 8W S Fixed WW 3 9S 2 lW 5 Fixed lK 1 4W 5 47C n 5 1 4W REGUlATORS 780SCP 7812CP 7906CP Diode Zener Pot Trim lOOn Card Ejector 9 13 SECTION 9 ASSEMBLY 99 402 01B OMRON PIN 80 311 55 80 319 06 80 311 56 80 319 01 80 258 03 80 251 18 80 211 02 80 214 71 80 464 02 80 464 03 80 464 05 80 403 08 80 270 15 40 109 10 ...

Page 237: ...80 319 002 c C1 C3 C2s 1SOUF 1sV Tant Dip 80 311 055 CIS 39UF 10V Tant 80 302 008 INTEGRATED CIRCUITS j XB1 XD4 7404 80 460 018 I XB3 XB4 74161 80 460 058 XBS 1489 80 460 084 XB6 1488 80 460 083 XC1 XC4 XF4 7400 80 460 022 XC3 7402 80 460 062 XCS 7432 80 461 054 XD2 XE1 XE2 7403 80 460 059 XF1 XG1 XD3 9386 80 460 088 XD6 74123 80 460 052 XE4 7442 80 460 031 XES 9314 80 461 029 XE6 XFS XG6 7408 80 ...

Page 238: ... 4W S SOCKETS 40 Pin Dip 14 Pin Dip 16 Pin Dip 16 Pin Dip Card Ejector Diode IN914 IN4148 Resistor Pack 2 2K 760 1 DESCRIPTION CAPACITORS 150UF 10WV Tant 01UF 100V 10 Cere Disc RESISTOR PACK 898 1 Rl30 330Q 893 3 R470 470Q 9 15 SECTION 9 ASSEMBLY 99 4S1 00lA OMRON PIN 80 211 003 80 212 071 80 213 031 80 212 021 80 212 023 80 675 010 80 676 003 80 676 004 80 676 001 40 109 009 80 404 003 80 290 051...

Page 239: ...01UF ioov Disc Cere INTEGRATED CIRCUITS 7400 74HOO 7402 7404 7406 7410 7420 7442 74 4 74H74 7492 74L02 74107 74121 74160 74161 74175 RESISTORS 27oQ 5 1 4W 2 7K S 1 4W 4 7K 5 1 4W 10K S 1 4W 15K S 1 4W 9 16 SECTION 9 ASSEMBLY 99 4S2 01C I OMRON PIN 80 311 55 80 320 87 80 302 08 80 319 01 80 320 93 80 460 22 80 460 35 80 460 62 80 460 18 80 460 73 80 460 19 80 460 17 80 460 31 80 460 34 80 460 77 80...

Page 240: ... SECTION 9 TIMING CONTROL CARD ASSEMBLY 99 452 01C DES tDESCRIPTION 1 OMRON PIN Yl Crystal 29 952 MHZ 80 967 93 CRl Diode IN914 80 404 03 Ejector 40 109 04 Ll Inductor 2 2UH 80 501 40 Ql Q2 Transistor 2N3904 80 422 11 9 17 ...

Page 241: ...CHARACTER GENERAL ROM Lower Case Upper Case PROM DIODES IN752A IN914 IN4148 INTEGRATED CIRCUITS 7400N 7402N 7403N 7404N 7410N 7420N 7427N 74H74N 7486N 74166N 74175N 74HOON 7408N 7432N 9 18 SECTION 9 ASSEMBLY 99 454 0LA OMRON PIN 80 320 93 80 311 55 22 003 035 22 012 07 80 404 12 80 404 03 80 460 22 80 460 62 80 460 59 80 460 18 80 460 19 80 460 17 80 460 61 80 460 77 80 460 54 80 460 63 80 460 64 ...

Page 242: ...0 211 00 Rl8 27ofl 1 4W 5 80 212 71 Rl7 33ofl 1 4W S 80 213 02 R3S R36 1IOl 1 4W S 80 211 02 Rl3 Rl9 56ofl 1 4W S 80 21S 61 R34 2 7K 1 4W 5 80 212 72 R20 1 5K 1 4W 5 80 211 52 Ejector 40 103 02 XAI Resistor Pack 1K 760 1 1K 13 80 290 60 J22 Socket 16 Pin Dip 80 676 04 Socket 24 Pin Dip 80 675 11 Q3 Transistor 2N4401 80 419 01 9 19 ...

Page 243: ...A si al from the terminal tells the modem that it wants to transmit data This signal allows the modem to prepare for data transmission by turning on the carrier if necessary allowing the carrier to stabilize and permitting the re mote carrrer to synchronize 10 1 4 Clear to S nd CB Pin 5 A signal from the modern in response to CA indicates that it is ready to receive data Various CB delays and opti...

Page 244: ...er On Signal Detector 9 Reserved Modem Testing 12V Positive Battery 10 Reserved Modem Testing 12V Negative Battery 11 Unassigned Not Used 12 SCF Secondary Receive Not Used Line Signal Detect 13 SCS Secondary Clear to Not Used Send 14 SBA Secondary Trans NS New Sync 1 1 Z mit Data 0 H 15 DB Transmitter Signal SCT Serial Clock Element Timing Transmitter 16 SBB Secondary Receive OCT Debit Clock Data ...

Page 245: ... BEL BL Bell BS Backspace CAN an Cancel CD DCL Character Delete CI ICL Character Insert CIF Character Insert Off CIN Character Insert On CLC EEL Clear Line from Cursor CR Carriage Return esc EED Clear Screen from Cursor DCl 01 Device Control 1 DC2 02 Device Control 2 DC3 03 Device Control 3 DC4 04 Device Control 4 DEL OT Delete DLE COL Data Link Escape EM End of Medium ENQ EQ Enquiry EO Eight Ones...

Page 246: ...r Left PM Cursor Pointer Return PP Previous Page PR CUF CUrsor Pointer Right PT Cursor Pointer Tab PU CUU CUrsor Pointer Up RLF Reverse Line Feed RS Record Separator SO Scroll Down S1 Shift In SO Shift Out SOH SH Start of Heading SP Space a blank STX SX Start of Text SU Scroll up SUB SB Substitute SYN SY Synchronous Idle US Unit Separator VT Vertical Tab VTC Vertical Tab Clear VTS Vertical Tab Set...

Page 247: ...l extension when preceded by BS Positions 2 7 and 2 12 are invariant but also serve as diacritical marks Presently known assignments are given in Table E 3 Page E 7 2 Columns 2 through 5 Define the ASCII 64 Character set 3 Columns 2 through 7 Define the ASCII 96 character set 4 Columns 2 through 9 Define the ASCII 128 character set S Columns 4 and 5 ESC CHAR 6 Columns 4 through 9 Soft Copy Contro ...

Page 248: ...ved by preceding a regular character with an ESCape 10 Hollerith card code for 256 characters 8 x 32 25 256 is constructed 12 1 or 2 or 3 or 7 or blank no punch 11 8 E any combination of 12 11 0 0 9 8 and 9 from none to all For historical reasons assignments present little in the way of a regular pattern but they are the key for translation to and from IBM EBCDIC ...

Page 249: ...M B 8m L Ii Ii 4 5 6 7 8 9 10 11 L mr l l _ El P HI co B CD n SB S B iiii 8 8iii 8 co El A 8B PU 0 B B0 0 III C Bill PIt 13 813 PI iii E 8IiI I BI 0 BO I M iii lSI 1 1 8 fiI PT J fiI J B 1iI El I iii K l1 13li Ci C 8 ill J iii il B u iii EI il B III SID iii l I il il 8 Ii CD I HI r 9 S Bm Blil CIH iI R b BID r 8 c BI m Ell i ill t Bill 5 0 I su I m 2 III JL 813 III Ii I II Itil 8 IHI EI IIii I I i...

Page 250: ...hange automatic send and receive transmitted data recdved data degrees Centigrade or Celsius request to send clear to send data terminal ready ring indicatQr received line signal detector centimeter central processing unit cathode ray tube direct current Department of Health Education and Welfare for example Electronic Industries AssQciation foot l8 mberts ground height logic 1 high voltage Hertz ...

Page 251: ...ut International Standards Organization keyboard 103 keyed send and receive character by character logic 0 pOlD ld light emitting diode 106 10 3 10 6 metal oxide semiconductor National Electrical Manufacturers Association 10 9 phase pulses per second programmed read only memory standard typewriter keyboard arrangement random access memory regulated read o ly memory second synchronization teletypew...

Page 252: ...LIST OF ABBREVIATI S ABBREVIATION V W dimensions DEFINITION volts width ...

Page 253: ...ron tube like a T V picture tube used for visual display CG data channel Channel for supplying refresh data to the video control card Character generator Memory device that stores the video dot pattern for character generation on the CRT display Character eeriod Time 670 nsec needed for one dot line in a character Clear memory Instruction to erase data in RAM memory CRT displal Device that visuall...

Page 254: ...on Memory seam Highest available address in memory Modem Device that modulates and demodulates signals transmitted over communications facilities Monitor Same as CRT display NAND gate Gate that has a low output when all inputs are high NOR gate Gate that has a low output when at least one input is high OR gate Gate that has a high output when at least one input is high pa e base Defines the memory...

Page 255: ...ers the refresh memory Read only memory ROM Permanent memo y n Whfch stored data can only be read Refresh memory Memory that stores information for use by a CRT display or other read devices RM data channel Olannel on which data leaves the refresh memory Screen Face of the CRT used in a CRT display Video modification Change to the normal presentation on the CRT display ...