AR0331
23
Dual Readout Paths
There are two readout paths within the sensor digital
block. The sensor PLL should be configured such that the
total pixel rate across both readout paths is equal to the
output pixel rate. For example, if CLK_PIX is 74.25 MHz
in a 4-lane HiSPi configuration, the CLK_OP should be
equal to 37.125 MHz.
Figure 21. Sensor Dual Readout Paths
CLK_PIX
CLK_PIX
Pixel Rate = 2 x CLK_PIX
= # data lanes x CLK_OP (HiSPi)
= CLK_OP (Parallel)
All Digital
Blocks
Serial Out-
put
(HiSPi)
Pixel Array
All Digital
Blocks
The sensor row timing calculation refers to each data-path
individually. For example, the sensor default configuration
uses 1100 clocks per row (line_length_pck) to output 1928
active pixels per row. The aggregate clocks per row seen by
the receiver will be 2200 clocks (1100 x 2 readout paths).
Parallel PLL Configuration
Figure 22. PLL for the Parallel Interface
EXTCLK
(6
−
48 MHz)
CLK_OP
(Max 74.25 Mp/s)
CLK_PIX
(Max 37.125 Mp/s)
F
VC0
pre_pll_clk_div
2(1
−
64)
pll_multiplier
58(32
−
384)
vt_sys_clk_div
1 (1,2,4,6,8,10
12,14,160
vt_pix_clk_div
6(4
−
16)
The maximum output of the parallel interface is 74.25
MPixel/s. This will limit the readout clock (CLK_PIX) to
37.125 MPixel/s. The sensor will not use the F
SERIAL
,
F
SERIAL_CLK
, or CLK_OP when configured to use the
parallel interface.
Table 12.
PLL PARAMETERS FOR THE PARALLEL INTERFACE
Parameter
Symbol
Min
Max
Unit
External Clock
EXTCLK
6
48
MHz
VCO Clock
F
VCO
384
768
MHz
Readout Clock
CLK_PIX
37.125
Mpixel/s
Output Clock
CLK_OP
74.25
Mpixel/s
