HTTP://BBS.FIXCLUB.COM.CN
9
JUL 2002
Edition 1.0
DP-1510P/1810P
/1810F/2010E
• Synchronization Control Circuit
This circuit is used to synchronize the output of the recorded data with the horizontal synchronizing
output signal from the printer for each line. The IPC controls the resolution of the printer as follows.
• FIFO/S-RAM Control
Picture Edit Coding Gate Array uses FIFO for Smoothing & Laser pulse width control, and S-RAM for
Smoothing Data and interface controls.
• Serial Communication Port for LP Interface
It provides 1ch Serial Communication Port interface for the Printer Mechanical CPU.
2. SORT Memory Control Gate Array
BRIDGE (DZAC000233) is a SORT Memory Control Gate Array and provides the data transfer control
function between Sort Memory Control, DANCE, CODEC for Image, and System.
• DMA Control
It is used to transfer the following data.
• S-DRAM Control
It generates S-DRAM Control Signal for SORT Memory and Refresh Control when the power is ON. it
does not backup the Page Memory.
3. PWM Control LSI
PM-1075 (IC26), which is a PWM control LSI, converts an 8-bit input digital signal into an analog signal
with 256-scale pulse width. The conversion allows modulation of pulse width in recorded data,
transferring the data to LSU, enabling multiple-value recording.
The pulse width is determined by the Picture Edit/Recording Gate Array (DANCE).
The function performs centering, reading, and trailing edge modulation in the pulse.
4. Optional Memory for Image Side
The Optional Memories are:
• Memory PC Board (SODIMM)
→
DRAM Card (8/16/128 MB) for Sort memory
Install the DRAM Card for Sort memory to CN151 on the SORT PCB.
16 dot/mm x 15.4 line/mm
:
Report data
15.4 dot/mm x 16 line/mm
:
Report rotation recording data
600 dpi x 600 dpi
:
Copy, Printer Interface & PDL Interface
Picture Edit/Recording Gate Array (DANCE)
←→
CODEC for Image (PM-22c) : Bus Selection
CODEC for Image (PM-22c)
←→
SORT Memory (S-DRAM)
: Compress, Restore
SORT Memory (S-DRAM)
←→
System Memory (DRAM)
: PC Scanning
