3DQDVRQLF
26
Chapter
3
EURO 4H Supplement
2.3.4. Output Formatter
The final processing stage of the VPC for the
luminance and chrominance signals is the formatter
stage here the signals are output from the VPC via
pins 20-25 / 28-29 for luma and 38-43 / 46-47 for
chroma in 4:2:2 format at 20.25MHz, synchronised by
the horizontal and vertical sync. signals output from
pins 12 and 14. Accompanying these vertical and
horizontal synchronisation signals is the active video
out (AVO) signal fed via pin 17 of the VPC IC1501,
which is fed to IC1502 where it is used to signal the
active video signal data output from IC1501.
2.3.5. Synchronisation Processing
Synchronisation is provided by the Sync. Processing
stage, the sync. information extracted from the
video/luma signal being distributed internally to the
rest of the video processing system.
Most of the processing that runs at the horizontal
frequency is programmed by an internal Fast
Processor (FP).
2.3.6. Control
In addition to those signals mentioned above the VPC
also provides the following clock frequencies.
:
LLC2 pin 18 - provides a 27Mhz clock which is
produced by the internal rate multiplier used to
synthesize the clock frequency of 27MHz used
as the system clock for the support of the 100Hz
system.
:
LLC1 pin 19 - provides a 13.5Mhz clock which is
used as the system clock for support of the 50Hz
system.
Control
of
the
VPC
is
performed
by
the
microprocessor IC1101 via I
2
C bus 2.
:
Serial data line SDA pin 55.
:
Serial clock line SCL pin 56.
Summary of Contents for EURO 4 Chassis
Page 24: ...3DQDVRQLF 24 ...
Page 26: ...3DQDVRQLF 26 TV STANDARDS ...
Page 93: ...3DQDVRQLF 10 ...
Page 97: ...3DQDVRQLF 14 Chapter 2 EURO 4 Supplement P Board DAF Circuit ...
Page 101: ...3DQDVRQLF 18 ...
Page 121: ...3DQDVRQLF 38 Chapter 3 EURO 4H Supplement Y Board Schematic ...
Page 124: ...3DQDVRQLF 41 ...
