3DQDVRQLF
30
Chapter
3
EURO 4H Supplement
2.5.1. Operation
The selected digitised luminance and chrominance
signals output from IC1502 via pins 10-17 (luma) and
pins 20-27 (chroma) are fed to the input of IC1503.
Here the luminance signal is input via pins 43-50 and
the chrominance input via pins 31-34 and 37-40.
These signals input to IC1503 being synchronised by
the vertical synchronisation pulse input pin 22,
horizontal synchronisation pulse input pin 23 and the
13.5MHz system clock signal input via pin 29.
This system clock of 13.5MHz also provides the
memory controller with a write clock, which is required
when writing the luminance and chrominance data
into the internal memory.
These luminance and chrominance signals are then
processed by the Low Data Rate (LDR) processing
stage for:
:
Noise reduction
:
Vertical compression
:
Horizontal compression
:
Motion detection
:
Movie mode detection
After undergoing this processing the luminance and
chrominance signals are then up-converted for 100 /
120Hz display by the High Data Rate (HDR)
processing stage. This up-conversion being achieved
by reading out the luminance and chrominance data
from the internal memory at twice the rate that the
data was written into memory.
To achieve this a 27MHz read clock is required by the
memory controller, this 27MHz system clock signal for
the 100 / 120Hz system being input via pin 54, is then
used to read data out of the memory at the increased
rate thus performing up-conversion.
In addition to this up-conversion the internal memory
and HDR stage also allow the display of a still picture.
These
now
up-converted
luminance
and
chrominance signals are then output from IC1503,
with the luminance signal being output from pins 1,
3-7, 63 and 64, while the chrominance signals are
output via pins 10-17. Here both the luminance and
chrominance signals are fed to IC1504, the final
processing IC on the F-Board.
To achieve the processing carried out by IC1503 the
following signals are also required.
2.5.2. Input Signals
:
SCL - pin 20
This is the serial clock input which is part of the I
2
C bus
1 control line.
:
SDA - pin 21
This is the serial data input which is part of the I
2
C bus
1 control line.
:
Reset - pin 30
The reset input which is an active LOW input, is used
to ensure correct operation after a power on. This is
achieved by keeping IC1503 in a stable condition
during this period.
2.5.3. Output Signals
:
CLKout - pin 26
This output provides the 27MHz clock signal which is
fed to IC1504 and used as the system clock to support
the processing of the up-converted luminance and
chrominance signals.
:
Hout - pin 60
Pin 60 of IC1503 is used to provide a horizontal
synchronisation signal used for further processing of
the up-converted luminance and chrominace signals.
:
Vout - pin 61
Output from pin 61 of IC1503 is a vertical
synchronisation signal used for further processing of
the up-converted luminance and chrominace signals.
Summary of Contents for EURO 4 Chassis
Page 24: ...3DQDVRQLF 24 ...
Page 26: ...3DQDVRQLF 26 TV STANDARDS ...
Page 93: ...3DQDVRQLF 10 ...
Page 97: ...3DQDVRQLF 14 Chapter 2 EURO 4 Supplement P Board DAF Circuit ...
Page 101: ...3DQDVRQLF 18 ...
Page 121: ...3DQDVRQLF 38 Chapter 3 EURO 4H Supplement Y Board Schematic ...
Page 124: ...3DQDVRQLF 41 ...
