Panasonic EURO 4 Chassis Technical Manual Download

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3DQDVRQLF

Chapter

EURO 4H Supplement

2.7.

Display Processing

The luminance and chrominance signals input to the
DDP IC1504 are fed via pins 54-61 (luma) and pins
43-50 (chroma), synchronised by the horizontal and
vertical synchronisation signals input via pins 63 and
64 respectivley. Here the 4:2:2 YC

signals on wide

screen models are fed via the horizontal scaler.

The horizontal scaler synchronised by the 27MHz
clock signal input via pin 53 is responsible for the
display of the active picture in a number of formats,
these being:

Just mode

4:3 mode

Like the scaler stage of the VPC IC1501 discussed in
chapter 3 section 2.2., the DDP scaler stage also
contains a programmable decimation filter, a 1-line
delay

FIFO

memory

and

programmable

interpolation filter.
The controlling of the scaler being performed by the
internal Fast Processor.

After the Horizontal scaler the luminance and
chrominance processing then splits into two paths.

2.7.1. Luminance Processing

The luminance signal passes via a number of control
stages such as the contrast control stage and
dynamic peaking circuit used to enhance the
luminance signal.
The luminance signal is then fed via a brightness
adjustment and soft limiter circuit. The soft limiter
circuit being used to prevent the CRT from being
driven to hard due to high contrast and brightness
levels, which in turn causes the beam current to
increase resulting in the CRT overheating producing
colouration.
Once the signal has been output from the soft limiter
the luma signal is fed to the matrix circuit for
production of the RGB signal.

2.7.2. Chrominance Processing

In the chrominance processing path the C

signals

are converted from 4:2:2 to 4:4:4 sampling rate. by the
interpolator stage before undergoing Digital Colour

Transient Improvement (DCTI).
The DCTI stage is used to sharpen the chrominance
rise time, which is achieved by applying a correction
signal that is calculated by differentiating the colour
difference signals. The amount of correction is limited
automatically. The C

signals are then input to the

matrix circuit where the luminance signal is added to
the C

signals to produce a digital RGB signal.

2.7.3. Tube Control Stage

After the RGB signals are output from the matrix
circuit, the signals are input to 3 multipliers which are
used to digitally adjust the white drive. The digital RGB
signals are then output as 10 bits of information. The
same multipliers are also used to implement a
software beam current control.
The digitised RGB signals, along with the display and
clock control data are then synchronised by the
Horizontal flyback pulse input via pin 9 of the DDP,
before the digitised RGB signals are fed to the
Analogue Backend which is the final processing stage
of the DDP.

Also included in the display processor stage of the
DDP IC1504 is the picture frame generator, which is
used when the picture does not fill the total area of the
screen (height or width to small). In this case the area
around the picture is surrounded with black bars,
generated by the frame generator.

2.7.4. Scan Velocity Modulation

The video RGB which is fed to the three multipliers is
also fed to the Scan Velocity Modulator (SVM) circuit,
here the RGB input signal is converted to a luminance
(Y) signal which is carried out by a simple matrix. The
analogue output signal is generated by an 8bit D/A
converter where the SVM signal is output via pin 23
of the DDP IC1504.

Here the SVM signal is fed via a transistor array which
amplifies and buffers the signal. This operation being
performed by transistors Q1504, Q1503 and Q1502
The SVM signal is then fed to the E-Board via
connector F1 pin 9 where the signal is fed directly to
the CRT drive stage located on the Y-Board.