S-8
S3.6. Power Block Diagram
IC1001
(7CH SW REGULATOR IC)
INV1
LX1
15
32
SCP
26
LX1
17
13
STB1
12
11
29
RT
31
21
V
CC
PV
CC
D2.9V
F1001
1
2
3
BATTERY
DC
JACK
1
3
8
5
4
BAT+
BAT-
Q1007
(MOS-FET: Nch)
6
5
4
3
1
2
QR1002
F1002
1
3
8
5
4
Q1008
(MOS-FET: Nch)
D1001
QR1005
QR1003
218
IC6001
(VENUS PLUS)
224
44
36
IC9101
(SYSTEM)
20
23
POWERSWON(L)
POWERSWON(H)
POWERSW
NACADP
POWERON
POWER SW ON
POWER ON H
34
1
8
IC6002
(FLASH ROM/128Mbit)
DSE
RE
33
RESETOUT
264
RSTB
132
RL6004
CPUREB
19 SW UNREG
177
ACADP DETECT
16
CH1
(N/Pch)
14
22
HX1
VBAT
PGND12
HX2
20
25
LX2
18
19
CH2
(N/Pch)
INV2
27
LX3
6
8
CH3
(N/Pch)
INV3
LX4
7
5
CH4
(N/Pch)
4
HX4
PGND34
NON5
PV
CC
5
2
35
OUT5
1
CH5
(Pch)
INV6
PGND567
43
36
LX6
44
CH6
(Nch)
INV7
38
OUT7
37
42
CH7
(Nch)
INV7I
34
SCP
10
ON/OFF
LOGIC
OSC
DMC-LZ3/LZ4/LZ5 POWER BLOCK DIAGRAM
UNREG
CL1008
CL1007
CL9088
2
MRES
RL6003
RL6054
5
18
46
V
DD
24
37
32
RESETIN
D2.9V
UNREG
SCP
STB2
STB3
STB4
5V
AF3.4V
CL1010
D1.2V
CCD12V
1
2
3
4
5
D
S
G
3
2
1
6
4
5
1
2
3
4
5
D
S
G
Q1070
(MOS-FET: Nch)
To CCD
(CCD MINUS)
QR1060
LCD8.5V
VREF
CL1030
CL1040
CL1051
CL1060
CL1070
IC9101-
(D2.9V)
32
RL6003 (SYS RESET)
RL6054 (CPU RESET)
RL6004 (CPURE)
2.0V 5msec./DIV
RL9105
Q1060
(MOS-FET: Pch)
PGND12
PGND34
HX3
9
INV4
28
PV
CC
PV
CC
PV
CC
PV
CC
HS6L
45
HS6H
46
ROOD
SW
HS7L
41
HS7H
40
ROOD
SW
PV
CC
PV
CC
VREF
48
47
STB5
STB6
39
STB7
23
UDSEL1
24
UDSEL2
3
UDSEL4
33
GND
REG A
30
VREGA
CL1001
CL1002
QR1001
RL9116
Q1005
(MOS-FET: Nch)
D1002
CL1020
Q1031
(MOS-FET: Nch)
Q1003
(MOS-FET: Pch)
Q1041
(MOS-FET: Nch)
To IC9101 - 34
(POWER ON H)
1
2
3
4
5
D
S
G
QR1041
PP9001
13,29
PP9001
26
ON
OFF
POWER SW
FLASH TOP P.C.B.
PS8001
26
PS8001
13,29
CL8012
IC3004 - 33
(CCD POWER)
D1004
D1050
D
S
G
D
S
G
D
S
G
D6001
IC7002
(REGULATOR)
1
2
6
OVER HEAT&
OVER
CURRENT
PROTECTION
CONTROL
CIRCUIT
BANDGAP
REFERENCE
3
4
VOUT
VIN
VCONT
GND
NP
5
GND
To IC7001
(A3.1V)