1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
G
NV-VZ14EG/EGE/EGM, NV-VZ15B/EG/EGE/EGM/EN, NV-VZ55EG/EGM
MONITOR SYSTEM BLOCK DIAGRAM
17
16
15
5
24
23
3
22
12
19
7
20
13
21
-
+
MODE SEL
V.SYNC
H.SYNC
FIELD
DET
POL
CTL
PHASE
COMP
SEL
QVD
EQ
PULSE
CANCEL
VCO
VCOI
36
QVD
34
PD
33
37
JUST
31
HDO
T2
30
CPH1
29
RL
28
CPH2
27
CPH3
25
STV2
26
24
STH2
STH1
23
22
QH
OEH
21
STV1
20
RESET
38
39
40
48
NC
18
OEV2
17
CPV
16
INT/EXT
15
POL
14
UD
13
NC
1
HD_IN
2 3
QH_SEL
4
VDB_IN
5
6
HD_OUT
NC
7
NC
8
12
CN7602
7
5
6
R7612
L7605
CLK1
RL
CLK2
STV2
CLK3
STH1
STH2
Q2H
OEH
STV1
CPV
R
G
B
SW
Q7607
ROUT
GOUT
BOUT
BUF&SW
Q7011
Q7013
BUF&SW
Q7015
BUF&SW
CLK1
RL
CLK2
STV2
CLK3
STH2
Q2H
STH1
STV1
OEH
CPV
R
G
B
LCD MODULE
RVS_SW
FROM DSP
LCD MONITOR
IC7603
COUNTER
ZOOM
CORRECT
18
15
16
25
18
15
16
25
VDCVF
HDCVF
DSP_REST
C7617
R7607
REG_3.2V
+
-
1
2
3
R7605
R7604
REG_15V
AMP
Q7601-Q7604
6
10
OSC
CTL
Q7504
Q7502
Q7501
Q7503
F7501
T7501
OSC
2
3
4
1
CTL
Q7504
Q7502
Q7501
Q7503
F7501
T7501
R7601,R7602
8
9
REG_15V
REG_3.2V
MREG_4.8V
VSS(REG_-15V)
L7604
L7601
2
11
10
1
MON_R
10
17
16
15
5
24
23
3
22
12
19
7
20
13
21
8
9
2
11
1
LCD (DAC_3.2V)
MONITOR
7
0
6
DSP_REST
FROM CPU
HDCVF
FROM DSP
VDCVF
5
LCD_CTL
FROM CPU
REG_4.8V
FROM REG
MAIN
1
0
12
MON_G
12
14
MON_B
14
CN16
CN7601
VDD
VEE
VSS
VGH
6
OEV
VGL
17
HRP1
17
REV_SW
HRP1
FROM CPU
TO DSP
LCD_CTL
REG_4.8V
REG_4.8V
CN7601
CN16
4
6
5
4
CFL
6
OEV
SW
Q7606
4
4
UD
TP7601
LT
NC
2
4
C7609
R7646
R7645
REG_3.2V
10
VCOM
C7622
10
-
+
Summary of Contents for NV-VZ14EG
Page 8: ...5 ADJUSTMENT PROCEDURES 5 1 DISASSEMBLY PROCEDURES Flow Chart for Disassembly Procedure 8 ...
Page 11: ...Fig 3 Fig 4 Fig 5 11 ...
Page 12: ...Fig 6 Fig 7 Fig 8 12 ...
Page 13: ...Fig 9 Fig 10 Fig 11 Fig 12 13 ...
Page 14: ...Fig 13 Fig 14 14 ...
Page 15: ...Fig 15 15 ...
Page 20: ...9 3 MONITOR SECTION 20 ...
Page 21: ...9 4 CAMERA LENS SECTION 21 ...
Page 22: ...9 5 EVF SECTION 22 ...
Page 23: ...9 6 PACKING PARTS ACCESSORIES SECTION 23 ...