Pin
No.
Mark
I/O
Division
Function
10
VREF+
I
Reference input
terminal
11
VDD
I
Power supply terminal
12
OSC2
I
System clock input
terminal (6MHz)
13
OSC1
O
System clock output
terminal (6MHz)
14
VSS
—
GND terminal
15
XI
I
Sub clock input terminal
(Not used, connected to
GND)
16
XO
O
Sub clock output terminal
(Not used, open)
17
MMOD
—
Memory mode select
terminal (Connected to
GND)
18
REM
DATA
O
LCD driver data output
terminal
19
LINK IN
I
Link serial communication
clock signal input terminal
20
—
—
Not used, open
21
SSDW
O
CPU interface data output
terminal
22
SSDR
I
CPU interface data input
terminal
23
SSCLK
O
CPU interface data clock
output terminal
24
BUZZER
O
Buzzer control output
terminal
25
RST
I
Reset signal input terminal
26
SELAD
O
CPU interface chip enable
output terminal
27
—
—
Not used, open
28
SE TR
O
Band pass filter set
terminal
29
—
—
Not used, open
30
BWCT
O
Band pass filter select
output terminal
31
INTB
I
CPU interface interrupt
input terminal
32
WRQB
33
REM
WUP
I
Remocon wake up
interrupt input terminal
55
Summary of Contents for SJ-MJ75
Page 9: ...9 ...
Page 10: ... Check the P C B A side as shown below 5 1 2 Checking for the P C B B side 10 ...
Page 11: ... To check the IC501 on side B of P C B refer to the table 1 and illustration below 11 ...
Page 12: ...12 ...
Page 13: ...5 2 Replacement for the intermediate cabinet Follow the Step 1 Step 3 of item 5 1 1 13 ...
Page 14: ...14 ...
Page 15: ...15 ...
Page 16: ...16 ...
Page 17: ...17 ...
Page 18: ...18 ...
Page 20: ...20 ...
Page 21: ...5 4 Replacement for the traverse motor Follow the Step 1 Step 3 of item 5 1 1 21 ...
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