TX-40ESR500
32
9 Block Diagram
9.1.
Main Block Diagram
LCD
Panel
T-CON
(DDR)
S1.5
S3.3
S1.0
(eMMC)
S1.8
STB1.05
S3.3
YPbPr
L/R in
CVBS
OPT
Head Phone L/R
Optical OUT
S3.3
eMMC
32Gb
Debug
Connector
A-SW
V-SW
ADC
[3:1]
RGB/YUV
Processor
ADC
DAC
ADC
VDOIN
DDR3
Controller
SD-IF
STB3.3
MT5581P
UART
UART-DMA(NonUse)
UART-DBG(Soft Debug)
IIC
VGA-IIC(NonUse)
24MHz
P15V
LVDS
Tx
S1.5
ATV
Decoder
USB-IF
ETHER-IF
FEAINP
FEAINN
Internal CI
controller
Low-IF
DEMOD
Wired OR
I2S(MCLK/LRCLK/BCLK/SDAT)
XRST/#AMP_MUTE
ADC
[0]
TV Decoder
CVBS VFE
VBI/COMB
SCART_CVBS
SAW
FLT
Digital CVBS
Digital SIF
Main
Sub
External Video(Analog)
External Video(HDMI)
Dec video
x32bit
1800MHz(DDR)
VDAC
Dec
Audio
SCART_CVBS OUT
SPI-IF
SCLK
SDI
SDO
CE#1
S3.3
IIC
BE_IIC0
BE_IIC1
I2S AMP
YDA176-QZ
(YAMAHA)
IFAGC2
IF1
(TU_Para_TS1)
uP
XRST
POWER_DET
<
TV_SOS
AMP/HP MUTE
MONITOROUT MUTE
P15V
STB5V
Analog
ASIC
OVP
SOS
Safety
Circuit
<
MON_MUTE
<
SP_HP_MUTE
PWMA
PWM_ENB
>
PWMOUT
Common-Reset
Paragon
Reset
Circuit
S3.3/1.8
SDVOLC
DDR3
4Gbx16
2pcs
MMCCLK
MMCCMD
XERST
MMCDAT0-7
eMMC-IF
MAIN
SUB
SPI-IF
Rx0
Rx1
Rx2
S3.3/ S1.2
DVB-T2
/T/C
DEMOD
1
<
FE_XRST
BE-IIC
41MHz
TU_Serial_TS1
(TU_Para_TS1)
EXT_IFAGC1
IF1
TU-IIC1
TU_Serial_TS1 / TU_Serial_TS1_JP
HDMI1.4
HDCP1.4
HDMI1.4
HDCP1.4
HDMI1.4
HDCP1.4
ARC OUT
Lch:10W
Rch:10W
S3.3/S1.8
Onboard
Single
Tuner
IFAGC2
EXT_IFAGC1
TU-IIC1
IF1
ETHER
10/100M
100Base-T
S5
IEEE802.11n
Wireless UNIT
USB2.0-IF
USB2.0-IF
HDD-USB
Power SW
For Wake up On Wireless
WOW_ON_IRQ <
< WOW_PWR_ON
> WOW_OVP
USB
Power SW
S5
USB*VBUS >
< OCP*
USB
Power SW
S5
USB*VBUS >
< OVCUR*
USB-1
USB-2
USB2.0-IF
USB2.0
(Port 0)
USB2.0
(port1)
USB2.0
(Port 2)
USB2.0
(Port3)
LED Information
G_LED_ON >
R_LED_ON >
<
㻌
KEY3
<
㻌
KEY1
CONTROL PANEL KEY
REMOCON
Reciever
LUMINANCE
Sensor
RMIN
>
AI_SENSOR
>
Main SW Soft Control
PANEL
Power
DCDC
PANEL_VCC_ON
P12
DDR3
x16
DDR3
DDR3
DDR3
DDR3
x16
DDR3
x16
CVBS
TV Encorder
DTV
Decoder
ATSC
DVB-T/C
SPDIF
SW
HDMI
Rx
MUX
x3
EDID1
EDID2
EDID0
Trans Port Demux
B2R
Video
MUX
AV Decoder
HEVC/ VP9
IMGRSZ
Scaler
3D/2D NR
Scaler
SCE
MUX
Color
Space
Convert
3D GPU
Graphic Processor
MUX
Gamma
Local
Dimming
OSD
Graphics
2Dto3D
Scannig PWM
UART
UART-PD(TK serial / uP Debug)
Standby CPU
8bit-CPU
Turbo8032
Host CPU
ARM Coretex-A7
Quad Core
924MHz
ARM
Non Use
Non Use
Non Use : SCART_RGB, FB, SLOW,
Head
Phone
Analog AV
Y
Pb
Pr
R
L
(CVBS)
Input
DDC2 > MT5581
HPD2 < MT5581
HDMI_5V_DET2 > MT5581
HDMI2
DDC1 > MT5581
HPD1 < MT5581
HDMI_5V_DET1 > MT5581
HDMI1
Audio
DSP
GPU
ARM Mali-450 432MHz
ARM11
For Audio
DATAIN[7:0]
CLKIN
SYNCIN
VAL_IN
DATAOUT[7:0]
CLKOUT
SYNCOUT
VALOUT
EA[14:0]
RESET
CE1/WE
OE/IOWR
IORD
IRQ
WAIT
CD1
CD2
DATAIN[7:0]
CLKIN
SYNCIN
VAL_IN
Transport
Stream
CI+
S5
CI
Power
Circuit
CI_POWER_ON
>
<
CI_OCP
LED Driver
BL_ON
>
BL_SOS
<
LVDS
P15
AUDIO OUT
Non Use
HP OUT
K-PCB
TX_P/N, RX
䠻
P/N
EEP
16k
STB-IIC
S3.3
DDC3 > MT5581
HPD3 < MT5581
HDMI_5V_DET3 > MT5581
HDMI3
* Only Australia/New Zealand
* Only UK/Continental/DACH
S3.3/ S1.2
DVB-T2
/T/C
DVB-S/S2
DEMOD
1
<
FE_XRST
BE-IIC
41MHz
TU_Serial_TS1
(TU_Para_TS1)
EXT_IFAGC1
IF1
TU-IIC1
SAT_AGC2
I_1
Q_1
DiSEqC1
S3.3/S1.8
Onboard
Single
Tuner
DiSEqC1
S15.7
LNB
BE-IIC
LNB
IFAGC2
EXT_IFAGC1
IEC
TU-IIC1
IF1
REG
<
ODU_ON
>
ODU_DET
I_1
Q_1
SAT_AGC2
AV2018
* For UK/Continental
* For DACH/New Zealand
S3.3/S1.8
Onboard
Single
Tuner
IFAGC2
IEC
IF1
* For Australia
#SOS
CEC
FHD model : Dual
HD model : Single
Non Use
COMP_DET
HP
Driver
24
䡮䢙䡽䛿
3W+3W
For Wake up On LAN
F
IEC
BCAS
Card I/F
CLK
RST
CLE
DATA
INT
S3.3
16MHz
Summary of Contents for TX-40ESR500
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