GRL-PCIE5-CEM-RXA User Guide and MOI
Rev7.0
© Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022
Page 34 of 123
5
Testing Using GRL-PCIE5-CEM-RXA Software
The GRL-PCIE5-CEM-RXA test solution supports automated Rx compliance testing as well as
optional SJ margin search testing for PCIe Gen 5 system board and add-in card DUT
’
s. Rx
compliance testing includes Tx preset test, initial Tx equalization test, Tx link equalization
response test, and Rx link equalization test performed at 32.0 GT/s. The GRL software will initially
run through link training with the DUT to prepare it for Loopback mode. Once the DUT is ready for
next transition state, the software will start to initiate loopback on the DUT and then measuring
the Bit Error Ratio (BER) using the calibration stressed signals. The Rx path is tested with worst
case eye to ensure a BER of less than 1E-12 can be achieved.
When testing is completed, the GRL software will generate a test report detailing all results
obtained from the test runs.
5.1
Overview of DUT Tx Preset Test
Note: This only applies for the add-in card DUT and is not required for the system board DUT.
The PCIe Gen 5 add-in card DUT will be tested for Tx preset compliance as defined by the PHY Test
Specification at 32.0 GT/s. This will first ensure the DUT is able to generate the correct Tx
equalization values for each of the total 11 presets before being tested for Tx equalization.
Note: This test requires the DUT to be in the polling.compliance state. No Variable ISI channel will be
used in the setup.
5.1.1
Add-In Card Tx Preset Test at 32.0 GT/s
The test setup should be based on the following:
•
Attach the add-in card DUT to the calibration revision 5.0 (for 32.0 GT/s) CBB with no
power applied.
•
Connect the compliance toggle outputs (MMPX connectors J5 and J85) on the CBB main
board to the Rx lane 0 (MMPX connectors J18 and J2) on the CBB.
•
Apply 50-ohm terminations on all Tx lanes other than the Tx lane under test.
•
Connect the Tx lane under test to the input of the oscilloscope. Make sure that the CBB is
supplying SSC enabled clock (-0.5% down-spread) for this test.
Once the CBB is powered on, set the CBB compliance toggle to initially place the DUT in the 32
GT/s test state and capture the following:
•
2.0 million unit intervals of data (2.0 x 10
6
x 31.25 ps = 62.5
μs
)
Save the captured waveform for the initial preset value, using a compliance pattern of 64 ones
and 64 zeros. Then, repeat the test for all 11 presets at 32.0 GT/s.
