GRL-PCIE5-CEM-RXA User Guide and MOI
Rev7.0
© Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022
Page 36 of 123
respond to commands to adjust the transmitter equalization values during link training for DUT
loopback.
5.3.1
System Board Tx Link Equalization Response Test at 32.0 GT/s
The test setup should be based on the following:
•
Attach the calibration revision 5.0 (for 32.0 GT/s) CLB to the system board DUT with no
power applied.
•
Connect the Rx lane under test on the CLB to the BERT signal source.
•
Connect the Tx lane under test on the CLB to the input of the BERT error detector.
•
Make sure that the Tx/Rx lanes other than the lane under test are unterminated.
Note the setup will not include any Variable ISI channel.
Once the system board DUT is powered on, it should start link training and negotiation to 32.0
GT/s. Send a command from the BERT to the DUT to set the Tx equalization to the following:
•
preset 0 (preshoot to 0.0 dB and de-emphasis to -6.0 dB)
Ensure that this Tx equalization transition is able to complete within a 1 microsecond response
timeframe. Record the cursors reported by the DUT for that preset.
Set the BERT error detector to place the DUT in the loopback state and capture the following:
•
2.0 million unit intervals of data (2.0 x 10
6
x 31.25 ps = 62.
5 μs)
Save the captured waveform for preset 0. Then, repeat the test with presets from P1 to P9.
Finally, read the saved waveform files and calculate the preset values using the SigTest
Transmitter Preset Test option. The test is considered as successful if all preset values are within
their allowable limit range as specified for 32.0 GT/s as well as able to complete within a 1
microsecond response timeframe.
The test should also be repeated with each request for the DUT Tx equalization using the cursors
reported by the DUT for that preset
.
5.3.2
Add-In Card Tx Link Equalization Response Test at 32.0 GT/s
The test setup should be based on the following:
•
Attach the add-in card DUT to the calibration revision 5.0 (for 32.0 GT/s) CBB with no
power applied.
•
Connect the Rx lane under test on the CBB to the BERT signal source.
•
Connect the 100 MHz reference clock output from the BERT to the clock input on the CBB.
•
Connect the Tx lane under test on the CBB main board to the input of the BERT error
detector.