GRL-PCIE5-CEM-RXA User Guide and MOI
Rev7.0
© Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022
Page 57 of 123
8.1.1
Calibration Settings
Configure the following settings to be applied for PCIe Gen 5 based Rx calibration.
T
ABLE
6.
C
ALIBRATION
S
ETTINGS
Component
Setting
PCIe Gen 5
Variable ISI Board
Insertion Loss (dB)
34-37
[a]
SigTest
CTLE Gain (dB)
9-15
[b]
MP1900A BERT
Tx Emphasis Preset
P5, P6, P8, P9
Amplitude (mV)
550
(800 mVpp-diff at output of Noise Module)
RJ (mUIpp)
180
SJ @100 MHz (UIpp)
0.1
DM-I (mV)
27
CM-I (mVpp)
170.0
[a]
The insertion loss measures in between 34 to 37 dB for all configurations using different variable ISI pairs
that provide the correct amount of insertion loss being measured.
[b]
The CTLE range from 9 dB to 15 dB in 1 dB step sizes is run for every waveform. (Note that this is a subset of
allowed CTLE range. This subset is used to reduce calibration time.)
The following table shows the calibration targets to achieve:
T
ABLE
7.
C
ALIBRATION
T
ARGETS
Setting
PCIe Gen 5
Amplitude (mV)
800
RJ (psrms)
0.5
SJ @100 MHz (mUIpp)
100 (at TP3)
DM-I (mVpp)
10 (at TP2)
CM-I (mVpp)
150
EH (mV)
13.5 to 16.5
EW (ps)
8.875 to 9.875
8.1.2
Calibration Process
Calibration for the PCIe CEM 5.0 electrical specification will basically be performed at two physical
test points: TP3 and TP2 (for the Long Channel). Test Point 3 (TP3) is a physical test point for
calibration without the effect of a channel. An adjustable CEM connector will be used along with
the calibration channel for testing the receiver. This will need to adjust the eye amplitude to