Pentek 52791, Getting Started Manual

Page 8

Model 52791 Getting Started Guide

Rev. 1.0

Timing and Synchronization (continued)

•

Reference clock: 

The front panel has one SSMC coaxial connector for a tuner 

reference clock input, labeled 

REF CLK

. The external reference clock signal must be a 

sine wave of 0.5 

−

 2.0 V

P

−

P

, with a frequency range from 12 to 30 MHz. This input is 

enabled using the Clock Control/Status Register REF CLK SEL bit. The front panel 

has one SSMC coaxial connector for a tuner reference clock output, labeled 

REF OUT

. 

The external reference clock output is a sine wave of 1 

−

 2.0 V

P

−

P

, with a frequency 

range from 4 to 30 MHz.

FPGA Digital Interfaces 

Model 78791 includes a Xilinx Virtex

−

7 FPGA. The FPGA serves as a control and status 

engine with data and programming interfaces to each of the onboard resources includ

−

ing the A/D converters and RAM memory. The FPGA is factory programmed by Pen

−

tek to implement the standard signal processing and control functions specified in the 

Model 71791 Operating Manual

. The Pentek GateFlow

®

 FPGA Design Kit facilitates inte

−

gration of user

−

created IP with the factory

−

shipped functions.

Option 104 

−

 PMC Connector

The 5201 VPX carrier provides one 64

−

pin PMC connector, designated 

J14

, on the car

−

rier PCB. These pins are directly wired from PMC 

J14

 to the VPX 

P2

 connector for user 

I/O.

NOTE:

The 

P14

 signals can be configured in the FPGA as either LVDS or LVTTL but 

in either case are limited to 2.5V for the VX330T, or 1.8V for the VX690T, and 
also cannot be driven with a negative voltage.

NOTE:

Refer to Section 2.9.6 of the 

Model 52791 Installation Manual

 for the pin 

mapping of the VPX 

P2

 connection.

Option 104 for the 71791 provides 48 pins (24 differential pairs) defined as 'User I/O' 

from the FPGA to PMC connector 

P14

. These connections are programmed for low

−

voltage differential signals (LVDS) in the default FPGA configuration. Refer to the sup

−

plied 

Model 71791 Operating Manual

 for a description of these signals.

Option 105 

−

 XMC Connector

The 5201 VPX carrier provides two XMC connectors, designated 

J15

 and 

J16

 on the 

carrier PCB. 

J15

 provides one x4 PCI Express link between the XMC and the carrier. 

J16

 provides one x8 or two x4 serial links between the XMC and the carrier for 71791 

Option 105 gigabit serial I/O.

The 5201 VPX carrier routes these data links from the XMC 

J15

 and

 J16

 connectors to 

the VPX 

P1

 connector.

NOTE:

Refer to Section 2.9.5 of the 

Model 52791 Installation Manual

 for the pin 

mapping of the VPX 

P1

 connection.