Perkin-Elmer M47-104, Maintenance Manual

Page 1: ...This is a reproduction of a library book that was digitized by Google as part of an ongoing effort to preserve the information in books and make it universally accessible https books google com ...

Page 2: ...INE AND 8 LINE COMMUNICATIONS MULTIPLEXORS MAINTENANCE MANUAL DEPOSITORY DEC 17 1984 UNIVERSITY OF ILLINOIS AT URBAN PERKIN ELMER Computer Systems Division 2 Crescent Place Oceanport N J 07757 Copyright 1978 by Perkin Elmer Corporation Printed in U S A August 1981 ...

Page 3: ...UNIVERSITY OF ILLINOIS LIBRARY AT URBANA CHAMPAIGN BOOKSTACKS ...

Page 4: ...d can be programmed for a variety of baud rates and character formats a 2 Chapter 1 contains general description of the COMM MUX Chapter contains the installation of the COMM MUX Chapter 3 contains the COMM MUX operations and maintenance information including block diagram analysis and a functional schematic analysis a The following manual provides programming information on the COMM MUX 2 Line an...

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Page 6: ... 3 2 2 3 3 2 3 4 INSTALLATION Unpacking Location Interrupt Priority Back Panel Wiring Cable Connections 2 1 2 1 2 2 2 2 2 4 O 2 4 ADJUSTMENT 2 4 2 5 2 5 1 5 2 OPTIONS 2 Line Communications Multiplexor Options 8 Line Communications Multiplexor Options 2 5 2 5 2 6 CHAPTER 3 OPERATION AND MAINTENANCE 3 1 3 1 INTRODUCTION 3 1 3 2 SCOPE 3 1 3 3 COMMUNICATIONS MULTIPLEXOR STATUS AND COMMAND BYTES 3 2 3 ...

Page 7: ...ICS 3 26 INDEX INDEX 1 FIGURES 0 Figure 1 1 Figure 2 1 Figure 2 2 Figure 2 3 Figure 2 4 Figure 2 5 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Figure 3 7 Figure 3 8 Communications Multiplexor Block Diagram 16 398 Half Board Adapter Standard Interrupt Priority 8 Line COMM MUX Board Top View Front Cable Routing Via Flat Cable Clamp COMM MUX Switch Positions Write Read Line Turn...

Page 8: ... Assembly Drawing 8 Line Functional Schematic 2 Line M01 Assembly Drawing 2 Line M01 Cable Assembly Common MUX Cable Assembly Line Common MUX Test 35 702R 12D03 35 702R 11EO 3 35 701 MO1ROS DOS 35 701MOIROS DO 3 17 46 3 MO 1R02CO3 17 514RO 1C03 29 650 R19 8 81 v vi ...

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Page 10: ...als The system conforms to the RS 232C interface and can be programmed for a variety of baud rates and character formats 1 2 SCOPE This document describes the installation and functional operation of the COMM MUX and provides useful maintenance information for digital technicians who maintain these devices A block diagram analysis and a functional analysis of major areas of each COMM MUX 2 line an...

Page 11: ...D 20 MA MILLIAMPERE CURRENT LOOP RS 232C DRIVERS RECEIVERS OR RATE TERMINAL GENERATOR MULTIPLEXOR BUS INTERRUPT AND STATUS GENERATOR MULTIPLEXOR BUS ADDRESS DECODE AND CONTROL LOGIC MODEM COMMAND REGISTER 2 LINE ONLY Figure 1 1 Communications Multiplexor Block Diagram 1 2 29 600 ROO 7 78 ...

Page 12: ...s slot via the 16 398 Half Board Adapter Kit Refer to Figure 2 1 Depending on requirements the half board adapter kit can strap two active 178 mm 7 boards or one active and one blank 178mm 7 board Wiring does not take place between the boards and the adapter Due to the adapter s design the connectors on the board plug directly into the chassis slot connector The 2 line COMM MUX 178 mm 7 half board...

Page 13: ...ng the module remove the applicable RACKO TACKO strap as explained in the following paragraphs 2 3 3 Interrupt Priority Back Panel Wiring The acknowledge control line from the processor carries the interrupt acknowledge ACK signal This line breaks into a series of short lines forming the daisy chain priority System The ACK signal must pass through every controller equipped with interrupt control c...

Page 14: ...n pin 122 9 and pin 222 9 or pin 122 0 and pin 222 0 of that slot must be removed from the back panel same As the 2 line COMM MUX may be installed in either the Oor 1 side of a chassis slot the location determines which jumper is removed from the selected chassis slot i e jumper 122 0 to 222 0 for the zero side or jumper 122 1 to 222 1 for the one side 1 The 8 line COMM MUX connects to both the O ...

Page 15: ...ugh a flat cable clamp secured to a bracket 14 531 on the left side of the mounted chassis looking from the front to the cable entry panel Refer to Figure 2 4 2033 BRACKET 14 531 FLAT CABLE CLAMP TO CABLE ENTRY PANEL Figure 2 4 Cable Routing via Flat Cable Clamp 2 4 ADJUSTMENT An oscillator and a strap option select the baud rate This procedure is described in Section 2 5 This adjustment is preset...

Page 16: ...4800 9600 300 1200 7200 19200 1 J6 to J9 J8 to J9 J6 open J8 to J9 J6 to J9 J8 open J6 open J8 open 0 J5 to 19 37 to J9 J5 open J7 to 19 J5 to J9 J7 open J5 open J7 open Half Full Duplex as required to select half of full duplex connect straps Channel Full Duplex In to I3 I 2 to 13 Half Duplex I 1 open 12 open o Address Interleaving If both channels are strapped for half duplex the board can be st...

Page 17: ...RNG To select 20 ma current loop Channel Function 0 ہ ے A6 to A7 A2 to A3 A 1 to A4 07 to D5 c7 to CO F1 to F2 F2 to F3 E6 to F3 A 5 E5 OPEN CS D4 E7 to E9 E8 to E9 E2 to E3 04 to 56 TRANSMIT DATA TRANSMIT DATA TRANSMIT DATA DUO DUO RECEIVE DATA RECEIVE DATA RECEIVE DATA B6 to B7 B2 to B3 B1 to B4 DO to D2 C3 to C2 F4 to F5 F5 to G1 F6 to G2 B5 G3 OPEN C4 D1 H1 to H3 H2 to H3 E1 to E3 01 to D3 Dis...

Page 18: ... 6 8 set status set the indicated To disable the following data switch to the ON position ES 2320 STATUS ܚ o 1 2 4 5 6 7 DSR A 160 3 A 150 5 A 122 1 A 122 2 A8 2 2 A8 2 5 A 25 1 A 25 6 CAR A 160 1 A 160 6 A 122 5 A 122 6 A82 1 A 82 6 A 25 4 A 25 5 CTS A 160 4 A 160 8 A 122 3 A 122 4 A8 2 3 A 82 7 A 25 2 A 25 8 ANG A 160 2 A 160 7 A 122 7 A 122 8 A 82 4 A 82 8 A 25 3 A 25 7 Address Interleaving To ...

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Page 20: ...d to set up take down supervise the data communications channel and provide proper status and interrupt information to the processor х The 2 line COMM MUX is contained on a 178mm x 381mm 7 15 board The 8 line COMM MUX is contained on a 381mm x 381mm 15 x 15 board The interface operation of the 2 line and the 8 line COMM MUX are similar therefore the block diagram and its explanation references bot...

Page 21: ...e in the receive side only It is reset at the next end of character only if the failure condition disappears i e is cleared by a read data instruction The character causing overflow is assembled and the previous character is lost PE is an In the read mode the priority fail FF status bit one when the received parity disa grees with the programmed parity If parity is not selected via output command ...

Page 22: ...e channel line from data set is active This bit is reset if the reverse channel line from data set is inactive If the data set dces not have the reverse channel option this status bit is always inactive Either transition of this signa 1 causes an interrupt if enabled BSY status bit is set one of If the busy BSY following occurs the 1 2 3 Data set ready DSR from the da ta set is inactive EX 1 Chara...

Page 23: ...sents the present state of the equivalent data set signal The COMM MUX needs two one byte commands COMMAND 1 BYTE refer to 3 5 2 In the COMM MUX Command 1 the DRT ECHO PLEX RCT DTB TRANS LB and WRT RD bits are shared by the transmitter and receiver However the EN DIS bits are separate for transmit and receive sides If the disable DIS Command bit is reset and the enable EN Command bit is set interr...

Page 24: ...ed data set requires RO2S to be active the data will not pass to the communication link This bit takes effect immediately Therefore a write to read with ECHO PLEX mode change requires transmitting X FF an ASCII DEL character as the last character RCT DTB The reverse channel transmit RCT Command bit is optional on 202C type data sets the data terminal busy DTB command bit to optional on 103 type da...

Page 25: ... normally programmed set except noted under DIS EN above COMMAND 2 BYTE refer to 3 5 2 CLKB CLKA CLK bits select one of four strapped baud rates Refer to Table 3 3 BIT SEL BIT SEL selects the number not including parity of data bits character BIT 11 10 0 0 0 NO OF DATA BITS 5 6 7 ک ے 0 1 1 1 8 If fewer than eight data bits are selected when a write data is issued in the write mode the data must be...

Page 26: ...bles the parity detection circuit NOTE 1 The least significant bit of the command byte must be a or 0 as indicated to permit the hardware to distinguish between the two Commands Command 2 should never be issued while data transfer is in progress 3 4 BLOCK DIAGRAM ANALYSIS and 35 702 Sheet 1 of Functional Schematics 35 701 2 line 8 line shows the block diagrams of the COMM MUX An oscillator provide...

Page 27: ...a instruction The programmed character format is applicable to the transmitter and receiver in the UART OV The UART receiver has three status bits PF and FR ERR They are updated immediately before busy goes inactive on the receive side The processor s Sense status instruction interrogates these status bits The RS 232C provides the logic level conversion between the TTL levels and the bipolar level...

Page 28: ...mpared with the programmed number of stop bits and parity error is detected one one or more appropriate status bits are set an In FDX operation data transfers may occur simultaneously This requires changing 2 line or switches 8 line in both directions the H Dx FDX straps format and baud rate To transmit to a data set the character must be loaded via an output command To select the mode an output c...

Page 29: ...he complete character is assembled pin 24 goes high generating an interrupt and dropping the BSY status to the processor At this time if an ov Pf or FR ERR has occured the appropriate output from the UART is high These status bits are only reset when another character is received without the error condition а that With BSY 0 the processor activates DRGO causing pin 24 responds with read data to go...

Page 30: ...ly one millisecond RQ2S to the data set is finally turned off After a delay in the data set CL2S turns off and the COMM MUX is not in the receive mode The BSY continues active until a character is received 3 5 2 LINE INTERFACE FUNCTIONAL SCHEMATIC DESCRIPTION 3 5 1 2 Line Multiplexor Bus Interface Functional Schematic 35 701008 multiplexor bus interface sections Sheets 2 and This interface 5 shows...

Page 31: ... to the scanner clock by the flip flop at 6L7 This flip flop delays the SYNC return to the processor until the internal interrupt scanner logic is at an update state 3 5 2 Commands Section 3 3 and the Communications Multiplexor Programming Manual Publication Number 29 654 show the command and status bytes Command 2 defined as D 150 true sets up the UART 19 081 the baud rate generator 19 239 and it...

Page 32: ... o 1 5 ODD 1 O 0 1 1 O ک ے 5 ODD 2 O 1 0 0 0 X 1 6 NONE O 1 1 0 X ه ے 1 6 NONE 2 O 1 0 1 1 6 EVEN ه ا o r 1 1 1 1 6 EVEN 2 1 0 1 0 ب ے 6 ODD 1 O 0 1 1 1 6 ODD 2 O 1 0 0 х 7 NONE 1 O o 1 X 7 NONE 2 0 1 ل ے 7 EVEN 1 o 1 1 1 7 EVEN 2 1 0 o ܝ 1 0 7 1 ODD ܝ 0 0 1 7 ODD 2 ہ ے 0 0 X 1 8 NONE 1 1 1 1 0 X 1 8 NONE 2 1 1 0 1 1 8 EVEN 1 1 1 1 8 EVEN 2 1 1 0 1 0 1 8 ODD 1 1 1 1 0 1 8 ODD 2 29 650 R 13 3 80 3 ...

Page 33: ...can be strapped and the 2 least significant bits 2LSB program selectable allowing program selection of 1 of 4 possible baud rates Refer to Section 2 4 ara TABLE 3 3 BAUD RATE SELECTION Strap Program Control Baud Rates 00 00 50 00 01 110 00 10 1 800 00 11 2 400 01 00 75 01 01 134 5 0 1 10 2 000 01 11 3 600 10 00 150 10 0 1 600 10 10 4 800 10 11 9 600 11 00 300 11 01 1 200 11 10 7 200 11 11 19 200 N...

Page 34: ...selected The transmitter contains a double character buffer A busy indicator is generated in the UART for each of these registers If the transmitter buffer register is empty pin 22 is high If the transmit shift register is empty pin 24 is high When pin 22 1 the processor issues a write data that causes DAGO to go low This parallel loads the buffer register and causes pin 22 to go low If the transm...

Page 35: ...TIL EOTO TRIES TO SET FOR NEXT CHARACTER ABOVE SHOWN FOR 8 LEVEL CODE PARITY AND TWO STOP BITS FOR NO PARITY STOP BITS FOLLOW DATA FCP ALL CODE LEVELS THE DATA IN THE HOLDING REGISTER IS RIGHT JUSTIFIED 4 5 Figure 3 3 UART Receiver Timing The UART received data input to pin 20 is normally high binary 1 When this line has a 1 to o transition the UART starts an interval timer that samples the data a...

Page 36: ... an interrupt on the receive side of a channel are input to a 19 157 NAND gate 8H5 9H5 to perform the OR function The one shot outputs that generate an interrupt on the transmit side are input to a 19 161 AND gate 8M8 9M8 followed by a 19 1 54 invertor 8N8 9 N8 to perform the OR function The receive interrupt channel X RINTX1 and transmit interrupt channel X TINTX1 outputs go to two input NAND gat...

Page 37: ... 3 4 2 Line Interrupt Block Diagram 3 5 5 Status The COMM MUX status word is defined in The Communications Multiplexor Programming Manual Publication Number 29 654 The status word is generated Ly to 1 multiplexors 19 177 3 A 6 3K6 The logic is shown below the multiplexors on Sheet 3 3 5 6 RS 232C Interface 2 line or 8 line Sheets 3 and 4 on 35 701 D08 2 line and sheets 14 through 17 on 25 702008 8...

Page 38: ...n These lines are data set ready DSRDY ring RING carrier CARR reguest to send RQ25 clear to send CL2S and data terminal ready DTR The logic conditions on these lines are described as being in the off or on condition as Figure 3 6 shows in Figure 3 6 shows the RS 232C electrical specifications relation to the mark space and off on conditions a A The communications multiplexor RS 232C transmitters h...

Page 39: ...chematic 35 702D08 multiplexor bus interface sections Sheets and 4 shows the This interface consists of 6 9 2 3 4 5 6 bus driver receiver data multiplexing address decoding control decoding SYNC return RACKO TACKO The bus driver receiver logic consists of bus transceivers 19 118 3E1 356 The internal bus inputs are from 4 to multiplexors 819 177 3B1 3B9 The multiplexor inputs are data status and in...

Page 40: ...ective UARTS and baud rate generators Sheets 10 through 13 Refer to Tables 3 2 and 3 3 for formats 8 8 Command 1 defined as D 150 false sets UP the interrupt conditions and the modem controls Sheet 8 shows the interrupt enable disable circuit BITS DO8 C09 MEANING 0 o 0 1 NO CHANGE ENABLE DISABLE DISARM ه س 0 1 When interrupts for a channel are enabled both the enable and gueue latches 19 140 for t...

Page 41: ... the shift register Pin 24 then goes low and the buffer register busy goes high At this time the processor loads another character The logic within the UART automatically loads the shift register at the correct time Refer to figure 3 2 for the transmitter timing diagram The UART receiver section performs the serial to parallel conversion on received characters and also test parity stop and start b...

Page 42: ... 19 173 Sheet 7 The output of the multiplexors are la tched by 19 167 7M2 738 The latched outputs reflect the current status state The current state is compared to the previous state that is la tched in the 19 041 register files Sheet 19 and the comparison logic is shown Sheet 7 If an interrupt condition is detected one of the 8 bit addressable latches for receive 18D 1 or for transmit 18 D5 is se...

Page 43: ...0308 8 TO 1 REGISTER LATCH MUX FILES INTERNAL 37 ADD MUX BUS LATCH INTERNAL DETECTION INTERNAL PRIORITY ENCODER CIRCUIT LATCH ATN FLIP FLOP Figure 3 7 8 Line Interrupt Block Diagram 3 24 29 650 ROO 7 78 ...

Page 44: ...AD21 SCAD31 SCADOD1 8 Line Tining Diagram LATCH MUXED STATUS ENABLE INT LATCH CLOCK INT FF Figure 3 8 WRITE INTO REG FILE 0 2 31 4 5 6 7 0 ENABLE INT CLEAR பு USED FOR CLEARING INT LATCH CLEAR ENABLE FOR LATCH 29 650 ROO 7 78 3 25 ...

Page 45: ...01D08 8 line source of each signal is also provided SCHEMATIC LOCATION MNEMONIC MEANING 2 Line 35 701 8 Line 35 702 209 3J6 3L8 ADO 1 ADL1 ADR00 01 ADR01 31 ADRSO 209 Board addressed signal Address latch load Latched address lines Latched address lines Address control line from the Processor Attention request line from a device to the multiplexor bus 201 3 E9 3J 1 ATNO 2E9 404 PA Shts 14 17 BAFLO1...

Page 46: ...onal 1 0 bus data lines Data available control line from the processor Decoded data available Decoded data available Data available strobe gated Internal data for 170 bus Latched carrier status from previous scan Latched clear to send status from previous scan Latched data set ready status from previous scan Delayed KACKO Data request control line from the processor Decoded data request strobe Lat...

Page 47: ... address Interrupt flip flop Receive side interrupt Source Transmit side interrupt source 6M7 18N2 404 7N6 7N9 LBOO 70 Line break Sht 9 2F9 MRACK0 1 MUX0 1 Internal receive acknowledge Select scan counter of interrupt address 4 F2 1809 GEO Cverrun error 535 TED Parity error 5 E4 Queue interrupts Sht 7 OU 001 011 101 111 IVE 11 JUNC 1 Queue even channel interrupts Queue odd channel interrupts Sht 8...

Page 48: ...SDSRO 1 SENO SI001 071 Shts 10 13 Sht 9 7N2 331 7B9 7N2 201 7K7 2B1 3L 1 RS 232C reverse channel transmit data RS 232C reverse channel received data UART status bits Interrupt scanner address bits Current carrier status System clear Current clear to send status Current data set ready status Transmit status enable Status control line from the processor Status control line from the Processor Current...

Page 49: ... acknowledge signal to next lower priority device on Multiplexor bus Transmit buffer empty Transmit buffer emtpy Terminal device unavailable 20 ma only Transmit channel interrupt Serial transmit data Shts 10 13 Sht 3 TINTO 1 11 TXD01 71 Shts 8 9 Shts 10 13 WR030 470 Write strobe for latched status 9 E9 3 30 29 650 ROO 7 78 ...

Page 50: ...4 Carousel 30 3 20 Carrier Off CARR OFF status bit control line 3 4 3 6 3 19 clear to Sent CL2S status bit control line 3 2 3 3 3 6 3 8 3 9 3 10 3 11 3 19 Clocks CLKB CLKA bits Command 2 3 6 Command bits 3 4 3 5 3 6 3 7 Command 1 byte DIS EN 3 4 DIR 3 5 ECHO PLEX 3 5 ECT CTB 3 5 TRANS LB 3 5 WPT RD 3 6 Command 2 byte CLKB CLKA 3 6 BIT SEL 3 6 STOP BIT 3 7 PAFITY 3 7 Communications multiplexor bloc...

Page 51: ...sfer 3 1 3 2 Disable Enable DIS EN bits Command 1 3 4 Device Unavailable TDU 3 20 Driver receiver bus 3 11 3 20 ECHO FLEX bit command 1 3 4 3 5 3 6 examine EX status bit 3 3 3 4 Flip flops SCADOD 3 16 3 23 SYNC 3 12 3 21 Spy FI 1 3 10 RTS 3 10 Interrupt 3 17 3 18 Framing Error FR ERP status bit 3 3 3 10 3 16 3 17 3 22 3 23 Full Duplex EDX i ii 9 1 2 1 3 1 3 4 3 6 3 8 3 9 3 10 Half Duplex HDY i ii ...

Page 52: ...mmand 1 3 4 3 5 3 19 Ring status bit 3 6 3 8 3 19 3 20 RS 232C Transmitters Receivers interface i ii 1 1 3 1 3 8 3 18 3 19 3 20 3 26 RTS flip flop 3 10 SCADOD flip flop 3 16 3 23 Signal lines Peceive Data RDATA 3 19 Reverse Channel Receive RCR 3 19 Reverse Channel Transmit RCT 3 19 Transmit Data TDATA 3 19 Status bits 3 2 3 3 3 4 Status byte OV 3 2 PF 3 2 CL2S 3 2 ER ERR 3 3 RCK 3 3 BS 3 3 EX 3 3 ...

Page 53: ...e turnaround 3 11 WRT RD bit Command 1 3 4 3 6 3 10 WAT flip flop 3 10 2 line communications multiplexor 178mm 7 half board installation 2 1 2 3 cabling 2 4 8 line communications multiplexor options 2 6 2 line communications multiplexor options 2 5 8 line communications multiplexor 381 mm 15 full board installation 2 1 2 4 cabling 2 4 Index 4 29 650 R05 5 79 ...

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Page 88: ...DIM A S EE TABLE 9 0 2 0 RIBS THIS SIDE NG 15 WIRE 1 T HIS SIDE S EE WIRING DIAGRAM WIRING Nimit 16 or 6 OI 21 SI bl 20 21 22 62 ININ 1 3M 24 25 26 27 28 29 30 31 32 33 WIRE 34 ir 12 001 gi 2 919 101 200 201 202 110 209 210 113 212 213 208 211 SIT 911 Siz giz 214 ROW 2 ROW 1 2 18 O PERKIN ELMER 1001 91 ir 00 19 POSITION 100 COVER Computer Systems Division Oceanport N J 07757 INFORMATION DISCLOSED ...

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Page 90: ...TING OFFICE s ťE NOTE 2 A 4 T YP I NSTA LL PER SSP 0 54 0 0 5 B PI STAMP 1 8 HIGH LETTERS STAMP PART NO APPROPRIATE REV LEVEL LEVEL P2 810 O o 1 5 9 2 9 15 USED IN MANUAL 29 650 8 VIE W B B WIR ING SIDE PERK IN E LME R VIE W A A WI RI NG SID E 1985 477 385 Computer Systems Division Oceanport N J 07757 7 UNLESS OTHERWISE SPECIFIED I NFORMATION DISCLOSED HEREIN IS THE PROP ERTY OF THE PERKIN ELMER C...

Page 91: ...UNIVERSITY OF ILLINOIS URBANA 3 0112 105111840 ...