IC Data Sheets
8.
Figure 8-2 Pin configuration
19160_301_110622.eps
110622
Pinning information
GP
IO
4
GP
IO
8
GP
IO
7
GP
IO
1
2
GP
IO
6
GP
IO
1
1
GP
IO
3
GP
IO
1
0
GP
IO
2
GP
IO
1
GP
IO
0
VC
C
3
IO
VC
C
K
GP
IO
1
3
PO
W
E_
PAAL
E
PAC
L
E
PO
C
E
1
_
PAR
B_
PO
O
E_
PO
C
E
0
_
PD
D
7
VC
C
3
IO
PD
D
6
PD
D
5
PD
D
4
PD
D
3
PD
D
2
PD
D
1
PD
D
0
CI
_
INT
GP
IO
GP
IO
GP
IO
VC
C
K
VC
C
3
IO
GP
IO
GP
IO
GP
IO
GP
IO
O
S
DA
2
O
S
CL
2
GP
IO
RF
_
A
G
C
IF
_
A
G
C
AO
L
R
C
K
AO
S
DA
T
A
0
AO
M
C
L
K
A
OBC
K
AO
S
DA
T
A
1
A
S
PD
IF
VC
C
K
VC
C
K
AR
1
_
AD
AC
AR
0
_
AD
AC
AL
1
_
AD
AC
AL
0
_
AD
AC
AV
SS
3
3
_D
A
C
AVD
D
33
_D
A
C
AVD
D
33
_A
A
D
C
AI
N
0
_
L
_
AAD
C
VM
ID
_
AA
D
C
AI
N
0
_
R
_
AAD
C
LO
U
T
P
256
255
254
25
3
252
251
250
249
24
8
247
246
245
244
24
3
242
241
240
2
3
9
2
38
2
3
7
2
3
6
2
3
5
2
3
4
2
33
2
3
2
2
3
1
2
3
0
229
22
8
227
226
225
224
22
3
222
221
220
219
21
8
217
216
215
214
21
3
212
211
210
209
20
8
207
206
205
204
20
3
202
201
200
199
19
8
197
196
195
194
19
3
FSRC_WR
1
192 AVDD33_XTAL_STB
GPIO14
2
191 XTALI
VCC3IO
3
190 XTALO
AVDD12_VPLL
4
189 AVDD33_DEMOD
AE5P
5
188 AVSS33_DEMOD
AE5N
6
187 AVSS12_DEMOD
AE4P
7
186 AVDD33_IFPGA
AE4N
8
185 ADCINN_DEMOD
AE3P
9
184 ADCINP_DEMOD
AE3N
10
183 AVDD12_DEMOD
AECKP
11
182 AVDD33_CVBS
AECKN
12
181 CVBS0P
AE2P
13
180 CVBS_COM
AE2N
14
179 CVBS1P
AE1P
15
178 SY0
AE1N
16
177 SC0
AE0P
17
176 SY1
AE0N
18
175 SC1
AVDD33_LVDSA
19
174 AVDD12_PLL
AVDD33_LVDSA
20
173 VCCK
AO5P
21
172 FS_VDAC
AO5N
22
171 AVDD33_VDAC
AO4P
23
170 VDAC_OUT1
AO4N
24
169 VDAC_OUT2
AO3P
25
168 AVSS12_RGB
AO3N
26
16 7 AVDD12_RGB
AOCKP
27
166 PR0P
AOCKN
28
165 PB0P
AO2P
29
164 COM0
AO2N
30
163 Y0P
AO1P
31
162 SOY0
AO1N
32
161 PR1P
AO0P
33
160 PB1P
AO0N
34
159 COM1
VCCK
35
158 Y1P
VCCK
36
157 SOY1
VCCK
37
156 RP
AVDD12_MEMPLL
38
155 COM
AVSS12_MEMPLL
39
154 GP
RODT//RCKE
40
153 SOG
RA8//RA10
41
152 BP
RA13//RBA1
42
151 HSYNC
RA11//RA4
43
150 VSYNC
RA4//RA1
44
149 AVDD33_VGA_STB
RA6//RA6
45
148 AVDD10_LDO
RA0//RA8
46
147 ADIN4_SRV
RA2//RA11
47
146 ADIN3_SRV
RCAS_//RA12
48
145 ADIN2_SRV
RCS_//RRAS_
49
144 ADIN1_SRV
RRAS_//RCAS_
50
143 ADIN0_SRV
RA9//RWE_
51
142 VC CK
VCC2IO
52
141 VGA_SCL
RA12//RA0
53
140 VGA_SDA
RA7//RA13
54
139 OPWRSB
RA5//RA9
55
138 OPCTRL1
NC//RRESET_
56
137 OPCTRL0
RA3//RA7
57
136 OIRI
RA1//RA2
58
135 U0TX
RA10//RA5
59
134 U0RX
RBA1//RA3
60
133 AVDD33_PDM_STB
RBA0//RBA2
61
132 OPCTRL2
RBA2//RBA0
62
131 OPCTRL4
RWE_//RCS_
63
130 OPCTRL3
RCKE//RODT
64
129 OPCTRL5
65
66
67
6
8
69
70
71
72
7
3
74
75
76
77
7
8
79
8
0
8
1
8
2
83
8
4
8
5
8
6
8
7
88
8
9
90
91
92
9
3
94
95
96
97
9
8
99
100
101
102
10
3
104
105
106
107
10
8
109
110
111
112
11
3
114
115
116
117
11
8
119
120
121
122
12
3
124
125
126
127
12
8
VC
C
K
RV
RE
F
RDQ
4
//RDQ
4
RDQ
3
//R
D
Q
6
VC
C
2
IO
RDQ
1
//RDQ
2
RDQ
6
//RDQ
0
RDQ
1
2
//RDQ
1
1
RDQ
9
//RDQ
9
VC
C
2
IO
RDQ
1
4
//RDQ
1
3
R
D
Q
11/
/R
D
Q
15
RDQ
M
1
//RDQ
M
1
VC
C
K
RDQ
S
0/
/R
D
Q
S
0
RDQ
S
0
_
//R
D
Q
S
0_
RDQ
M
0
//RDQ
M
0
VC
C
2
IO
RDQ
S
1/
/R
D
Q
S
1
RDQ
S
1_/
/R
D
Q
S
1_
R
D
Q
15/
/R
D
Q
12
RDQ
8
//R
D
Q
1
4
VC
C
2
IO
RDQ
1
0
//RDQ
1
0
RDQ
1
3
//R
D
Q
8
RDQ
7
//RDQ
1
RDQ
0
//RDQ
3
VC
C
2
IO
RDQ
2
//RDQ
7
RDQ
5
//RDQ
5
VC
C
2
IO
RCL
K
0
//RCL
K
0
R
C
LK
0_/
/R
C
LK
0_
VC
C
K
JT
D
O
JT
C
K
JT
M
S
JT
D
I
JT
R
S
T_
OP
W
M
0
VC
C
3
IO
VC
C
K
U
S
B_
2
P_
D
M
1
U
S
B_
2
P_
D
P
1
U
S
B_
2
P_
D
M
0
U
S
B_
2
P_
D
P
0
AVD
D
33
_U
S
B
_2P
U
S
B_
2
P_
V
R
T
AVD
D
33
_H
D
M
I
RX
_
CB
RX
_
C
RX
_
0
B
RX
_
0
RX
_
1
B
RX
_
1
RX
_
2
B
RX
_
2
AVD
D
1
2
_
H
D
M
I
HDM
I_
CE
C
HDM
I_
S
DA
HDM
I_
S
CL
HDM
I_
HP
D
PW
R
5
V
OR
E
S
ET
_
MT5301BCMU