Circuit-, IC descriptions and list of abbreviations
9.
Pin #
Name
Description
Output Signals
65-72
G/YOUT
9-0
Green or luminance output bus. In the RGB mode this output is the Green signal and in the
75-76
YCbCr mode it is the Y signal. The mode is set by the OFORMAT
2-0
pins. This can be
overridden by the OFmtOvr bit, bit 3 in register 07
H
, allowing this function to be set or
changed via the I
2
C bus. Please refer to the description of register 07
H
for details. The signal
is clocked out on the falling edge of YCLKO.
93-94
B/CbOUT
9-0
Blue or Cb chrominance output bus. In the RGB mode this output is the Blue signal, in the
97-104
Y Cb Cr mode it is the Cb signal. The mode is set by the OFORMAT
2-0
pins. This can be
overridden by the OFmtOvr bit, bit 3 in register 07
H
, allowing this function to be set or
changed via the I
2
C bus. Please refer to the description of register 07
H
for details. The busses
used in the multiplexed modes are set by means of bit 5 in register 08
H
. The signal is clocked
out on the falling edge of YCLKO in the RGB and YUV 4:4:4 modes, on the falling edge of
YCLKO prior to the next rising edge of CCLKO in the YUV 4:2:2 mode, and on the rising edge of
MEMCLKO in the multiplexed YCbCr (pseudo D1) mode.
77-83
R/CrOUT
9-0
Red or Cr chrominance output bus. In the RGB mode this output is the Red signal, in the
86-88
YCbCr mode it is the Cr signal. The mode is set by the OFORMAT
2-0
pins. This can be
overridden by the OFmtOvr bit, bit 3 in register 07
H
, allowing this function to be set or
changed via the I
2
C bus. Please refer to the description of register 07
H
for details. The busses
used in the multiplexed modes are set by means of bit 5 in register 08
H
. The signal is clocked
out on the falling edge of YCLKO in the RGB and YUV 4:4:4 modes, on the falling edge of
YCLKO prior to the next rising edge of CCLKO in the YUV 4:2:2 mode, and on the rising edge of
MEMCLKO in the multiplexed YCbCr (pseudo D1) mode.
116
CCLKO
Chroma output sampling clock. This clock is derived from PIXCLK and will be at half the
frequency of YCLKO. In 30-bit 4:2:2 output mode the chroma output signals will change on
the falling edge of YCLKO prior to the next rising edge this clock.
117
YCLKO
Luma output sampling clock. This clock is derived from PIXCLK and is double the
frequency of PIXCLK. In 30-bit and 20-bit output modes the output signals will change on the
falling edge of this clock.
89
VREFO
Start of active field or frame indicator. This signal goes high to indicate the first active line
in each field or frame and goes low during the vertical blanking interval. The polarity and timing
of this signal are programmable.
90
HREFO
Start of active line indicator output. This signal goes high to indicate the first active pixel in
each line and goes low during the horizontal blanking interval. The polarity and timing of
this signal are programmable.
91
VSYNC/
Vertical sync output. This signal provides the vertical sync function for the outputs. Its
CREFO
polarity is programmable to be active high or active low. It can also be programmed to be a
composite reference for applications requiring this instead of sync.
92
H/CSYNCO
Horizontal or composite sync output. This signal provides the horizontal sync function for
the outputs. Its polarity is programmable to be active high or active low. This signal can also
be programmed to be the composite sync output, CSYNC.
108
FSYNC
Film mode sync output. When film mode is detected this pin will toggle in sync with the 3:2
(NTSC) or 2:2 (PAL and 30 Hz film in NTSC) pulldown sequence detected in the source.
110
FILM
Film mode detector output. This pin will be set high when the FLI2200 detects that the video
input was converted from 24 fps film with a teleciné machine. If film mode is not detected this
pin will be set low.
Summary of Contents for DVDR70/001
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