The prescaler is a dual modulus type with programmable division ratios of either 64 or 65. If
the prescaler were of the fixed division ratio type (eg: divide by 64), then the frequency steps
that may be programmed by incrementing the programmable divider by 1 would be in steps of
64; the total divider chain changing its division ratio by a factor of 64. To program a channel
spacing of 25kHz, it would then be necessary to use a reference frequency Fr, of 25kHz/64 =
390Hz.Such a low reference frequency is undesirable because it results in a slow responding
loop to frequency changes, less than optimum noise performance, and large division ratios
(eg: l0MHz reference oscillator would require a division ratio of 25,600 which is not possible
with the NJ8822).
In operation, the dual modulus prescaler division ratio is toggled dynamically by the
programmable divider IC403 at PIN 1 of IC402 using +5V CMOS logic. The prescaler's input is
at PIN 6 and the divided output appears at PIN 3.
IC403 is the programmable divider and phase comparator IC. The division ratio for both the
reference divider and the main frequency dividers are set by a sequence of serial data
commands from the microprocessor. The programming inputs at Pins 12, 13 and 14 are serial
data, serial clock and chip enable respectively. The programmed data is latched into IC403
and is only updated if a new frequency division is required, or if an out-of-lock state exists.
This state appears as a logic high +5V at PIN 4 of IC403. The data is clocked in with a cycle
time of approximately 5uSec. The entire data stream occurs in a burst of approximately
150uSec duration. When the loop is out of lock the re-programming occurs every 40mSec.
During the burst of data the chip enable input at PIN 14 is held high.
The high gain sample and hold phase comparator has adjustable gain which is set by an
external resistor R518 at PIN 17 and capacitor C522 at PIN 15. These components are
optimized for each frequency band of the phase locked loop operation. The output of this
phase comparator appears at PIN 1 of IC403.
A digital phase/frequency comparator provides for a coarse adjustment of the loop until the
VCO frequency is brought within the narrow capture range of the high gain phase comparator.
When this happens the output goes into a tri-state condition and appears as a high
impedance.
3.2.3.5
LOOP FILTER
The output of the analog and digital phase comparators at PINS 1 and 2 of IC403 are
combined at the summing input of the loop filter IC404 is a dual low noise operational amplifier
half of which is configured as a low pass filter.The design of this filter determines many of the
performance aspects of the phase locked loop. The major aspects being loop cut-off
frequency, damping factor, reference frequency suppression, and noise performance. The
loop filter is relatively simple and is used primarily to establish the loop dynamics and not to
suppress the reference frequency products out of the phase comparator. This is due to the
high quality of suppression already achieved by the analog phase comparator in IC403.
Although the digital phase comparator at PIN 2 becomes high impedance when in lock, diode
D436 is required to isolate the loop filter from any noise residuals of IC403.
Section 3 Page 14
