When the primary supply voltage drops below 9.8V, the voltage drop across D225 allows
R300 to forward bias TR224. TR224 and TR232 form a Schmitt trigger with R395 providing
hysteresis and C302 providing speed up. As TR224 collector voltage rises, TR232 also
conducts, reinforcing TR224 forward bias. TR225 is biased on, generating a logic low (0 volt)
on the microprocessor interrupt input PIN 8. During this interrupt state, the majority of the
microprocessor ports are set low and the microprocessor is configured in a low current
consumption standby mode. All operational aspects of the radio are also disabled.
The instant at which the interrupt active low output occurs, TR232 collector switches low. This
causes TR226 to forward bias and its collector raises the base voltage of TR227, to ensure
that the RESET output at the collector of TR227 remains low. This mechanism ensures that
the RESET is never active during the time the interrupt is active for the power failure condition.
The low collector voltage of TR232 also causes C299 to discharge via D227 and R302.
Immediately following the initial supply voltage application TR224 switches off. TR225 and
TR232 also switch off, and the interrupt control to the microprocessor becomes inactive
(+5.2V). The RESET output at the collector of TR227 switches to active high (+5.2V). This is
held for 120mSec until C299 charges. During the RESET period with interrupt high and reset
high, the microprocessor output ports are configured to logic high.
Upon initial power application conditions may occur where the interupt becomes active low
until the supply voltage has increased sufficiently to switch off TR224. In this case the RESET
output must be held high. TR233 is active during the initial power-up and ensures that TR226
is biassed off and, thereby, TR227 conducts for the period of the time constant set by C299.
If a supply voltage interruption occurs during the 120mSec RESET period, TR224, TR232 and
TR226 are instantly switched on, causing the RESET output at the collector TR227 to switch
low. C299 is also discharged and will re-initialize the 120mSec timer for the RESET output
pulse. The interrupt output is delayed following the reset by R394 and C298 to allow the
microprocessor to prepare for the interrupt.
3.2.4.4
CLOCK
The 16MHz clock signal for the control microprocessor is derived from the crystal oscillator
composed of TR211, XL201 and associated components. The frequency of this oscillator can
be shifted approximately 500ppm by switching the crystal capacitance via TR212 and C281.
Control of this switching is by the central control processor on a per channel basis via the
serial latch IC207 pin 12. Oscillator switching is provided to reduce possible receiver
desensitisation due to harmonics from the 16MHz clock and its associated subharmonics.
The buffered output of the clock from the control processor is fed to IC211 and is then divided
by 16 to produce the 1 MHz clock required by IC204, the CTCSS encoder/decoder.
Later models will have a 12MHz clock oscillator, which requires different hardware and
software.
Section 3 Page 20
