Circuit Descriptions, Abbreviation List, and IC Data Sheets
EN 50
TES1.0E LA
9.
9.5
IC Data Sheets
This section shows the internal block diagrams and pin layouts
of ICs that are drawn as "black boxes" in the electrical diagrams
(with the exception of "memory" and "logic" ICs).
9.5.1
Video Processor with CPU Core, STV3550 (U601)
Figure 9-3 Internal block diagram and pin configuration of the Video Processor
Block Dia
g
ram
Pin Confi
g
uration
G_16510_05
8
.ep
s
221106
H100
V100
Output
4- to
YCRCB[7:0]
VSYNC
Clock
Generator
2D
Bl
oc
k
OS
D
STV3550
Mo
ve
HSYNC
27 MHz
CLK_DATA
CLKXTM
CLKXTP
Clock
External
Memory
Interface
Flash
SDRAM
Video
Display
Pipeline
PSI/CTI
Standard Definition
Input (SDIN)
H/V Filter
Temporal Noise Reduction
Film Mode Detection
Picture
Compositor
Cursor Plane
Background Plane
Gamma Correction
Digital
Video
Output
Perfect Color
Engine
TV Peripherals
I/O Ports, 4 Timers,
UART, WDT, PWM
and Infrared Digital
Preprocessor
DCLK
DE
Time
ba
s
e
Ge
ne
ra
to
r
RGB
Vi deo
Outputs
Reset
10-bit
ST20 32-bit CPU Core
4 kB I-Cache 4 kB D-Cache
Interrupt Controller
Diagnostic Controller
100 MHz, 8 kB SRAM
SD
RAM_
D
2
SD
RAM_
D
1
SD
RAM_
D0
S
D
RAM_
D
1
5
S
D
RAM_
D1
4
S
D
RAM_
D
1
3
S
DRAM_
D
1
2
S
D
RAM_
D
1
1
S
D
RAM_
D
1
0
SD
RAM_
D9
SD
RAM_
D8
DE
VDD18_CORE
VSS_IO
VSS_IO
VDD33_IO
P_VIDEO0
P_VIDEO1
P_VIDEO2
P_VIDEO3
P_VIDEO4
VDD33_IO
P_VIDEO5
VDD33_IO
NC
VSS_IO
ADDR_13
NOT_BE1
ADDR_12
ADDR_11
ADDR_9
ADDR_8
ADDR_7
ADDR_6
ADDR_5
V
DD
33_I
O
FL
AS
H_
D1
1
FL
AS
H_
D3
FL
AS
H_
D1
0
FL
AS
H_
D2
FL
AS
H_
D9
FL
AS
H_
D1
FL
AS
H_
D8
FL
AS
H_
D0
V
D
D
33_I
O
VS
S_
IO
POR TC0
PORTA0
PORTD4
PORTA1
POR TD7
PORTA4
VDD33_IO
PORTA5
POR TA6
PORTA7
VDD33_IO
VSS_IO
POR TD5
PORTC7
PORTC6
PORTC5
POR TC4
PORTD0
PORTD1
POR TD2
PORTD3
VDD33_IO
PORTD6
POR TA2
PORTA3
VSS_IO
PORTB5
PORTB4
PORTB3
PORTB2
PORTB1
PORTB0
VDD33_IO
VCC33_ADC
GND_ADC
SHIELD_ADCDAC
V100
H100
CLK_DFL
DCLK
VSS
_I
O
P_
VI
DE
O
6
P_
VI
DE
O
7
P_
VI
DE
O
8
P_
VI
DE
O
9
P_
VI
DE
O10
P_
VI
DE
O11
P_
VI
DE
O12
P_
VI
DE
O13
P_
VI
DE
O14
V
D
D3
3
_
IO
P_
VI
DE
O15
P_
VI
DE
O16
P_
VI
DE
O17
P_
VI
DE
O18
P_
VI
DE
O19
VSS
_
IO
P_
VI
DE
O20
P_
VI
DE
O21
P_
VI
DE
O22
P_
VI
DE
O23
P_
VI
DE
O24
VD
D
1
8
_
C
O
R
E
VS
S
V
DD
33_
IO
P_
VI
DE
O25
P_
VI
DE
O26
P_
VI
DE
O27
P_
VI
DE
O28
P_
VI
DE
O29
VSS
_
IO
V
DD3
3
_
IO
VS
S
VD
D
18
_
C
O
RE
SD
RAM_
D7
SD
RAM_
D
6
SD
RAM_
D5
SD
RAM_
D4
SD
RAM_
D3
ADDR_4
CKOUT_SDRAM
VDD33_IO
VSS_IO
CKIN_SDRAM
ADDR_3
ADDR_2
ADDR_1
ADDR_0
ADDR_10
ADDR_16
VDD33_IO
ADDR_15
NOT_CS_SDRAM
NOT_RAS
NOT_CAS
RD8NOTWR
NOT_BE0
VDD18_CORE
VSS
VDD33_IO
VSS_IO
NOT_CS_FLASH
ADDR_17
ADDR_18
ADDR_ 19
ADDR_14
VDD18_CORE
VSS
FL ASH_D15
FL ASH_D7
FLASH_D14
VDD33_IO
FL ASH_D6
FL ASH_D13
FLASH_D5
NC
FL ASH_D12
NC
FLASH_D4
TM
S
TC
K
TD
O
TDI
TRS
T
NRES
E
T
V
D
D
33_I
O
VS
S_
IO
V
D
D
18_C
O
R
E
V
C
C
18_I
O
GND_
IO
V
C
C
18_P
L
L3
GND_
PL
L
3
XT
AL
OUT
XT
AL
IN
V
C
C
18_P
L
L1
GND_
PL
L
1
CL
K
X
T
M
CL
KXT
P
VSS
_
P
LL
VDD1
8
_
IO
S
H
IE
LD
_P
LL
VSY
N
C
HSY
N
C
CL
K
_
D
A
T
A
YCRCB
0
YCRCB
1
YCRCB
2
YCRCB
3
YCRCB
4
YCRCB
5
YCRCB
6
YCRCB
7
V
D
D
33_I
O
V
D
D
18_C
O
R
E
VS
S_
IO
PO
R
T
C3
POR
T
C2
POR
T
C1
V
D
D
18_C
O
RE
157
208
52
104
1
53
105
156
STV3550
PQFP 280 Package
VSS
_I
O
VD
D
3
3
_
IO
VSS
_
IO