Bus Configuration for I/O Modules (RAD-ISM-900-EN-BD-BUS only)
2476_en_I
PHOENIX CONTACT
5-17
5.5.2
Analog Channel Scaling
Analog channels are scaled as follows:
5.5.3
Pulse Input Channels
If the input channel is set to frequency mode, the value displayed in the corresponding
register will be the input signal frequency in Hz (0-32 kHz).
If the pulse input channel is set to counter mode, each channel will have a 32-bit register
(two consecutive 16-bit registers) assigned to it. The first (LSW) register keeps the current
count (up to 32,767). To manually reset a channel to zero (0), simply write a “1” to the coil
register that corresponds to that channel. Refer to the address map in this section to
determine the correct register. A channel is reset to zero when the coil transitions from a “0”
to a “1.”
5.5.4
Pulse Output Channels
If the output channel is set to frequency mode, the value entered in the corresponding
register will be the output signal frequency in Hz (0-32 kHz). In frequency mode, the only
register that will respond to PLC commands is the least significant word (LSW). Because
the most significant word (MSW) exceeds the maximum pulse frequency that the module
can produce, any values written to it will be ignored.
If the pulse output channel is set to counter mode, each channel will have a 32-bit register
(two consecutive 16-bit registers) assigned to it. The counter mode has two different types
of operations: (1) absolute count and (2) differential count. The two modes are described in
the following paragraphs.
Absolute Mode
Pulses produced = New pulse count - Previous pulse count
In absolute mode, the total number of pulses provided is equal to the pulse output register
value.
For example, if the previous value in the register was 5 and a new value of 15 is written, 10
pulses will be produced. However, if a new value of 3 were written, the pulse module would
produce enough pulses to wrap the 32-bit register around until it is reset to 0 and then
deliver 3 more pulses. Therefore, the pulse register should be cleared periodically.
Current Input =
(Register Value) • 22 mA
32767
Current Output =
(X mA) • 32767
22 mA
NOTE:
If a pulse input channel is set to counter mode, you may need to periodically reset the
register to prevent overflow. To reset a channel to zero, simply write a “1” to the coil
register that corresponds to that channel. Refer to the address map to determine which
register. A reset command is executed when the coil transitions from a “0” to a “1.”
RSPSupply - 1-888-532-2706 - www.RSPSupply.com
http://www.RSPSupply.com/p-12970-Phoenix-Contact-2900016-Radio-900-MHz-Ethernet-Radio.aspx