Appendix A: Technical Specifications
Appendix A
Technical Specifications
Chipsets
Core Logic
North Bridge - Intel 945G.
South Bridge – Intel ICH7R.
Peripheral I/O
Standard Microsystems (SMSC) SCH311x.
BIOS
System BIOS
American Megatrends AMIBIOS8.
Flash BIOS
Standard feature for System BIOS. Flash programming built into the BIOS. BIOS to be flashed is read from a
floppy.
Embedded I/O
Floppy
2 Floppies up to 2.88 MB.
IDE
Single channel PCI 32-bit EIDE controller – UDMA 66/100 supported. One Standard 40-pin and one mini-
Header 44 pin for Solid State IDE disk or any 44 pin IDE device support.
Parallel ATA IDE Interfaces
The ICH4 Parallel ATA IDE controller has one independent bus-mastering Parallel ATA IDE interface that
can be enabled. The Parallel ATA IDE interface supports the following modes:
•
Programmed I/O (PIO): processor controls data transfer.
•
8237-style DMA: DMA offloads the processor, supporting transfer rates of up to 16 MB/sec.
•
Ultra DMA: DMA protocol on IDE bus supporting host and target throttling and transfer rates of
up to 33 MB/sec.
•
ATA-66: DMA protocol on IDE bus supporting host and target throttling and transfer rates of up
to 66 MB/sec. ATA-66 protocol is similar to Ultra DMA and is device driver compatible.
•
ATA-100: DMA protocol on IDE bus allows host and target throttling. The ICH ATA-100 logic
can achieve read transfer rates up to 100 MB/sec and write transfer rates up to 88 MB/sec.
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Summary of Contents for MicroATX Express
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