PCM-072/phyCORE-AM64xx System on Module
L-860e.A0
© PHYTEC America L.L.C. 2022
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A current sense amplifier that amplifies the voltage difference, making it easier to measure
Figure 16. SOM current reader reference circuit
5.2
To keep the Real-Time Clock (RTC) module running, a secondary voltage source of 3V can be supplied to the phyCORE-
AM64xx SOM at the VBAT pin (pin B4 of phyCORE-Connector X1). For the RTC to maintain time when main system power
is removed, the VBAT input must be supplied with power. The RTC draws 40 nA at 3V and is the only draw on VBAT. For
more information regarding the recommended operating voltage of the Backup Power Source VBAT, refer to
5.3 Reset
Several reset inputs and outputs are accessible at the phyCORE-Connector as listed in
X_MCU_RESETz, and X_RESET_REQz can be driven low to trigger cold/warm resets of different domains without cycling
power on the carrier board. We recommend designing reset buttons into your system that will tie the reset signals to
ground when pressed, allowing for manual control over system reset. These buttons can later be depopulated for
production purposes but are generally useful during board bring up and verification.
The X_PWR_EN signal is connected to the enable pin of the PMIC and will prevent the PMIC from starting when pulled
low. The X_MCU_RESETSTATz, X_RESETSTATz, X_PORz_OUT, and X_PGOOD signals are status outputs. PGOOD indicates
when the SOM power is stable and X_MCU_RESETSTATz / X_RESETSTATz / X_PORz_OUT are status outputs for
X_MCU_RESETz / X_RESET_REQz / X_nRESET_IN respectively.
Table 13 Reset Pin Description
X1 Pin #
Signal
Type
Level Description
B5
X_PWR_EN
I
5V
Enable pin for PMIC
B6
X_nRESET_IN
I
3.3V
Cold system Reset
B8
X_MCU_RESETz
I
3.3V
1
Warm Reset of MCU Domain
B11
X_RESET_REQz
I
3.3V
1
Warm Reset of MAIN Domain
B7
X_MCU_RESETSTATz
O
3.3V
1
MCU Domain Reset Status Output
B10
X_PORz_OUT
O
3.3V
1
Cold Reset Status Output
B12
X_RESETSTATz
O
3.3V
1
MAIN Domain Reset Status Output
