35
CDX-P1250
7. GENERAL INFORMATION
7.1 IC
-
Pin Functions (UPD63710GC)
Pin No.
Pin Name
I/O
Function and Operation
1
GND
Logic circuit GND
2
HOLD
I/O
Defect detection output
3
MIRR
I/O
MIRR output
4
FOK
O
RFOK signal output
5
rst
I
Reset signal input
6
A0
I
Command/parameter identification signal input
7
stb
I
Data strobe signal input
8
sck
I
Clock signal input for serial data input/output
9
SO
O
Serial data and status signal output
10
SI
I
Serial data input
11
VDD
Positive power supply terminal to logic circuit
12
DA.VDD
Positive power supply terminal to D/A converter
13
NC
Not used
14, 15
DA.GND
D/A converter GND
16
NC
Not used
17
DA.VDD
Positive power supply terminal to D/A converter
18
R+
O
Right channel audio data output
19
R-
O
Right channel audio data output
20
L-
O
Left channel audio data output
21
L+
O
Left channel audio data output
22
X.VDD
Positive power supply terminal to crystal oscillation circuit
23
xtal
O
Crystal oscillator connect pin
24
XTAL
I
Crystal oscillator connect pin
25
X.GND
Crystal oscillation circuit GND
26
VDD
Positive power supply terminal to logic circuit
27
EMPH
O
Output pin for the pre-emphasis data in the sub-Q code
28
FLAG
O
Flag output pin to indicate that audio data currently being output consists
of noncorrectable data
29
DIN
I
Serial data input to internal DAC
30
DOUT
O
Serial audio data output
31
SCKIN
I
Serial clock input to internal DAC
32
SCKO
O
Audio data that is output from DOUT changes at rising edge of this clock
33
LRCKIN
I
LRCK signal input to internal DAC
34
LRCK
O
Signals to distinguish the right and left channels of the audio data output
from DOUT
35
WDCK
O
Output double the frequency of LRCK
36
TX
O
Digital audio interface data output
37
GND
Logic circuit GND
38
C16M
O
Oscillator clock buffering output
39
LIMIT
I
Status of the pin is output at Bit 5 of the status output
40
VDD
Positive power supply terminal to logic circuit
41
LOCK
O
EFM synchronous detection signal
42
RFCK
O
Frame synchronous signal of XTAL-system
43
WFCK
O
Frame synchronous signal of PLL-system
44
PLCK
O
Monitor pin of bit clock
45
GND
Logic circuit GND
46
C1D1
O
Output pin for indicating the C1 error correction results
47
C1D2
O
Output pin for indicating the C1 error correction results
48
C2D1
O
Output pin for indicating the C2 error correction results
49
C2D2
O
Output pin for indicating the C2 error correction results
50
C2D3
O
Output pin for indicating the C2 error correction results
51
VDD
Positive power supply terminal to logic circuit
Summary of Contents for CDX-P1250
Page 6: ...6 CDX P1250 2 2 EXTERIOR ...
Page 8: ...8 CDX P1250 2 3 CD MECHANISM MODULE ...
Page 14: ...14 CDX P1250 1 2 3 4 1 2 3 4 D C B A A2 2 A 1 2 SYSTEM CONTROLLER EWmodel UC ESmodel ...
Page 22: ...22 CDX P1250 1 2 3 4 1 2 3 4 D C B A SIDE A B POWER UNIT B CN701 A CORD 4 2 POWER UNIT IP BUS ...
Page 23: ...23 CDX P1250 D C B A 1 2 3 4 1 2 3 4 B POWER UNIT B SIDE B ...
Page 25: ...25 CDX P1250 D C B A 1 2 3 4 1 2 3 4 E 4 5 MOTOR PCB MOTOR PCB E C ...
Page 30: ...30 CDX P1250 Grating waveform 45 0 75 60 30 90 Echt Xch 20mV div AC Fcht Ych 20mV div AC ...
Page 48: ...48 CDX P1250 7 3 BLOCK DIAGRAM A C D E ...
Page 49: ...49 CDX P1250 B ...
