70
-
Pin Functions (PE5352B)
Pin No.
Pin Name
I/O
Format
Function and Operation
1
BSO
O
C
P-Bus serial data output
2
bsck
I/O
/C
P-Bus serial clock input/output
3, 4
DFS1, 2
O
C
DA I/F IC sampling frequency setting output 1, 2
5
DCKS
O
C
DA I/F IC clock subharmonic number selection output
6
EVDD
E power supply Positive power supply
7
EVSS
E power supply GND
8
dspok
I
DSP microcomputer initialization OK input
9
DCOPY
O
C
DA I/F IC copy flag setting output
10
crst
O
C
Compression IC reset control output
11, 12
NC
Not used
13
EMPH
O
C
Emphasis information output
14
emph
O
C
Emphasis information output
15
DSPMUTE
O
C
DOUT mute output
16
DSET
O
C
Disc set indicator lighting output
17
adena
O
C
A/D reference voltage supply control output
18
IC/VPP
IC : VSS direct connection/VPP : Pull-down
19
BRXEN
I/O
/C
P-Bus reception is possible
20
bsrq
I/O
/C
P-Bus service request demand
21
xtalen!
O
C
CD LSI 16.9344MHz oscillation permission output
22
xtalen@
O
C
CD LSI 24.576MHz oscillation permission output
23
xrst
O
C
CD LSI reset control output
24
VDCONT
O
C
VD power supply control output
25
CD3VON
O
C
CD +3.3V power supply control output
26
CONT
O
C
Servo driver power supply control output
27
xwait
I
CD LSI wait control signal input
28
LOEJ
O
C
The direction change output of LOAD/EJECT
29
CLCONT
O
C
Driver input change output
30
CDMUTE
O
C
CD mute control output
31
reset
I
System reset input
32
XT1
I
Connected to the oscillator for subclock
(connected to VSS via the resistor)
33
XT2
Connected to the oscillator for subclock (Open)
34
REGC
Connected to the capacity stabilizing output of the regulator
(an electrolytic capacitor of about 1
µ
F)
35
X2
Oscillator connection for mainclock
36
X1
I
Oscillator connection for mainclock
37
VSS
GND
38
VDD
Positive power supply (5V)
39
CLKOUT
O
C
Internal system clock output (Open)
40
xwrite
O
CD LSI write control signal output
41
uben
O
Not used (Open)
42
WR/W
O
WMA decoder Read/Write control signal output
43
xread
O
CD LSI read control signal output
44
XASTB
O
CD LSI address strobe output
45
LOCK
I
Spindle lock input
46
wrst
O
C
WMA decoder reset control output
47-54
AD0-7
I/O
/C
Address/Data bus 0-7
55
BVDD
B power supply Positive power supply (3.3V)
56
BVSS
B power supply GND
57-64
AD8-15
I/O
/C
Address/Data bus 8-15
65
xcs
O
C
CD LSI chip selection output
66
wcs
O
C
WMA decoder chip selection output
67, 68
DBBWRDY0, 1
I
Input of write-ready flag with WMA decoder DBBI0, 1
69, 70
DBBRRDY0, 1
I
Input of read-ready flag with WMA decoder DBBO0, 1
71
AVDD
A power supply Positive power supply (5V)
72
AVSS
A power supply GND
73
AVREF
The reference voltage input for A/D converter
74
VDSENS
VD power supply short sense input
75
DSCSNS
Disc state sense input
76
TEMP
Temperature information sense input
1
2
3
4
1
2
3
4
F
E
D
C
B
A
DEH-P550MP/XN/UC
Summary of Contents for DEH-P550MP
Page 4: ...4 DEH P550MP XN UC 1 2 3 4 1 2 3 4 F E D C B A DEH P550MP XN UC 1 SPECIFICATIONS ...
Page 5: ...5 DEH P5500MP XN UC 5 6 7 8 F E D C B A 5 6 7 8 DEH P550MP XN UC ...
Page 6: ...6 DEH P5550MP XN ES 1 2 3 4 1 2 3 4 F E D C B A DEH P550MP XN UC ...
Page 7: ...7 5 6 7 8 F E D C B A 5 6 7 8 DEH P550MP XN UC ...
Page 10: ...10 1 2 3 4 1 2 3 4 F E D C B A DEH P550MP XN UC 2 2 PACKING DEH P5550MP XN ES ...
Page 12: ...12 1 2 3 4 1 2 3 4 F E D C B A DEH P550MP XN UC 2 3 EXTERIOR ...
Page 15: ...15 5 6 7 8 F E D C B A 5 6 7 8 DEH P550MP XN UC ...
Page 37: ...37 5 6 7 8 F E D C B A 5 6 7 8 DEH P550MP XN UC ...
Page 40: ...40 1 2 3 4 1 2 3 4 F E D C B A DEH P550MP XN UC A A TUNER AMP UNIT ...
Page 41: ...41 5 6 7 8 F E D C B A 5 6 7 8 DEH P550MP XN UC A SIDE B ...
Page 76: ...76 1 2 3 4 1 2 3 4 F E D C B A DEH P550MP XN UC 8 OPERATIONS ...
Page 77: ...77 5 6 7 8 F E D C B A 5 6 7 8 DEH P550MP XN UC ...
Page 78: ...78 1 2 3 4 1 2 3 4 F E D C B A DEH P550MP XN UC ...
Page 79: ...79 5 6 7 8 F E D C B A 5 6 7 8 DEH P550MP XN UC ...
