62
MJ-L5, SP-L5
No.
Name
I/O
1 to 7, 100
P96 to P90, P97 I/O
8
BYTE
I
9
CNVss
I
10
P87
I/O
11
P86
I/O
17
P85
I
18 to 22
P84 toP80
I/O
12
RESET
I
13
XOUT
I
15
XIN
O
14
Vss
––
16
Vcc
––
23 to 30
P77 to P70
I/O
31 to 38
P67 to P60
I/O
39 to 46
P57 to P50
I/O
WRL/WR,
O
WRH/BHE,
O
RD,
O
BCLK,
O
HLDA,
O
HOLD,
I
ALE,
O
RDY
I
47 to 54
P47 to P40
I/O
CS3 to CS0,
O
A19 to A16
O
Description
These are 8 bit I/O ports with the same functions as P0. By software selection, it functions as the input terminals
for the timers B0 to B2, the output terminals for the D/A converter, the expansion input terminals of the A/D
converter, or the A/D trigger input terminals.
This is the terminal for switching the external data bus width. When the level of this terminal is "L", the width
is 16 bits, and when it is "H", the width is 8 bits. Please fix it to one of these levels. At the time of single-chip
mode, connect it to the Vss terminal.
This is the terminal for processor mode switching. At the time of single-chip mode or at the time of memory
expansion mode, connect it to the Vss terminal. At the time of microprocessor mode, connect it to the Vcc
terminal.
P80 to P84, P86, and P87 are I/O ports with the same functions as P0. By software selection, they function
as the I/O terminals for the timer A4 or the input terminals for external interrupt. P86 and P87 function by
software selection as the I/O terminals for the subclock oscillation circuit. In this case, connect a crystal
oscillator between P86 (XCOUT terminal) and P87 (XCIN terminal). P85 is an input-only port serving also as
NMI. When the input of this terminal changes from "H" to "L", and NMI interrupt is generated. The NMI function
can not be cancelled by software. A pullup resistance can not be set for this terminal.
When the input to this terminal is "L", the microcomputer is reset.
This are the I/O terminals of the main clock oscillation circuit. Connect a ceramic oscillator or a crystal oscillator
between the terminals XIN and XOUT. In case of an externally generated clock, enter the clock from the XIN
terminal and leave the XOUT terminal open.
Impress 0 V.
Impress 2.7 V to 5.5 V.
These are 8 bit I/O ports with the same functions as P0. By software selection, they function as the I/O terminals
for the timers A0 to A3.
These are 8 bit I/O ports with the same functions as P0. By software selection, they function as the I/O terminals
for the UART0 and UART1.
These are 8 bit I/O ports with the same functions as P0. By software selection, they put out a clock with 1/8
or 1/32 of XIN or with the same cycle as XCIN from P57.
WRL, WRH, (WR, BHE), RD, BCLK, HLDA, and ALE signals are put out. Switching between WRL and WRH
and between BHE and WR is possible by software.
At the time of WRL, WRH, RD selection
When the external data bus width is 16 bits and the WRL signal is at "L" level, writing is done to an even
address, and the WRH signal is at "L" level, writing is done to an odd address. Reading is performed when
the RD signal is at "L" level.
At the time of WR, BHE, RD selection
Writing is done when the WR signal is at "L" level. Reading is done when the RD signal is at "L" level. An
odd address is accessed when the BHE signal is at "L" level. Please use this mode when the external data
bus width is 8 bits. The microcomputer is in hold status while the input level to the HOLD terminal is "L".
During hold status, the output from HLDA is at "L" level. ALE is the signal for address latching. The
microcomputer is in ready status while the input to RDY is at "L" level. A clock with the same frequency as
the internal clock ø is put out from the BCLK terminal.
These are 8 bit I/O ports with the same functions as P0.
The A16 to A19 and CS0 to CS3 signals are put out. A16 to A19 are the upper 4 bits of the address. CS0 to
CS3 are the chip select signals, and they are used for specification of the access space.
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Pin Function
