19
PD-30-K
5
6
7
8
5
6
7
8
A
B
C
D
E
F
MEMORY DATA 192K/12K SI
N
GLE CHIP MICO
N
• Block Diagram
• Pin Arrangement
Port P0
Additional function
Timer (16 bits)
Output (Timer A) 3 line
Input (Timer B) 3line
W
atch dog timer
(15 bits)
A/D converter
(10 bits x 1
8
channel)
M16C/60 series CPU core
Memory
System clock genarate
XI
N
-XOUT
XCI
N
-XCOUT
UART or Clock sync
serial I/O
(3 channel)
CRC operation circuit (CCITT system)
(generation many clauses expression:
X
16
+ X
12
+ X
5
+ 1
DMAC
(2 channel)
8
Port P1
8
Port P2
8
Port P3
8
Port P4
8
Port P5
8
Port P6
8
P
or
t P7
8
Po
rt
P
8
8
Po
rt
P
8
_5
8
P
or
t P9
8
P
or
t P10
8
R0H
R0L
R1H
R2
R3
A0
SB
I
N
TB
PC
USP
ISP
FLG
ROM
RAM
multiplier
A1
FB
R1L
(M3030SFEPGP)(MAIN PCB ASSY: IC3001)