PDP-501MX, PDP-V501X
74
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Pin Name
HRD
VDD 1
SWC1
SRC
SDP
SWC05
IE1
WE1
STROBE
VCC 2
HRA/BLNA
VSS 1
LLA
IE2
WE2
CLV
HVCD
RE1
RE2
BLND
ALE
WRD
VCC 2
VSS 2
P0
P1
P2
P3
P4
P5
P6
P7
LLDFL
VSS 3
HRDFL
VDD 4
HDFL
VDFL
VACQ
TEST
SSC
RSTW1
LLD
VSS 4
TYPE
O
S
O
O
I
O
O
O
I
S
I/O
-
I
O
O
O
O
O
O
O
I
I
S
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
-
O
S
O
O
I
I
I
O
I
-
Pin Function
Horizontal reference signal output (display PLL)
Supply voltage 1
Serial write clock output for memory 1
Serial read clock output
Select deflection processor input
Serial write clock output,SWC1 divided-by-2
Input enable signal output (memory 1)
Write enable signal output (memory 1)
Strobe signal input
Supply voltage 2
Horizontal reference signal output (acquisition part)/horizontal blanking signal input,reset
for horizontal acquisition counters(acquisition part)
Ground 1
Line- locked cloack signal input (acquisition part)
Input enable signal output (memory 2)
Write enable signal output (memory 2)
Horizontal signal output (acquisition part)
Horizontal,vertical or composite blanking signal output (display part)
Read enable signal output (memory 1)
Read enable signal output (memory 2)
Horizontal branking signal output (display part)
Address latch enable signal input
Wrirw/read data signal input
Supply voltage 3
Ground 2
Data input/output signal bit 0
Data input/output signal bit 1
Data input/output signal bit 2
Data input/output signal bit 3
Data input/output signal bit 4
Data input/output signal bit 5
Data input/output signal bit 6
Data input/output signal bit 7(MSB = Most Significant Bit)
Line-locked clock signal input (deflection part)
Ground 3
Horizontal reference signal output (deflection part)
Supply voltage 4
Horizontal synchronization signal output (deflection part)
Vertical synchronization signal output (deflection part)
Vertical synchronization signal input (deflection part)
Test input
Select signal clock system input
Reset write signal output (memory 1)
Line-locked clock signal input (display part)
Ground 4
¶
Pin Function
Summary of Contents for PDP-501MX
Page 16: ...PDP 501MX PDP V501X 16 A B C D 1 2 3 4 1 2 3 4 3 3 POWER SUPPLY MODULE 1 2 J 1 2 ...
Page 17: ...PDP 501MX PDP V501X 17 A B C D 5 6 7 8 5 6 7 8 J 1 2 ...
Page 18: ...PDP 501MX PDP V501X 18 A B C D 1 2 3 4 1 2 3 4 3 4 POWER SUPPLY MODULE 2 2 J 2 2 ...
Page 19: ...PDP 501MX PDP V501X 19 A B C D 5 6 7 8 5 6 7 8 J 2 2 ...
