PDP-507XD
196
1
2
3
4
1
2
3
4
C
D
F
A
B
E
Pin Function
2.3 I2C bus interface terminal
Acronyms
Terminal number
I/O
Level
Buffer type
PU/PD [k
Ω
]
Functions
RGRED
75
O
LVTTL
N-ch open drain
6 mA
I
2
C register lead flag output (Active-Low)
SCL
71
I
LVTTL
Fail-safe
I
2
C bus clock input
Connect to the SCL line of the system.
SDA
72
I/O
LVTTL
N-ch open drain
Fail-safe
6 mA
I
2
C bus data input/output
Connect to the SDA line of the system.
SLA0
73
I
LVTTL
–
I
2
C bus slave address selection input
(L : B8h/B9h, H : BAh/BBh )
Connect to GND when set to low level and to
DVDD3 (3.3V) when set to high level.
2.4 Terminal for test
Acronyms
Terminal number
I/O
Level
Buffer type
PU/PD [k
Ω
]
Functions
SCKSET
2
I
LVTTL
–
Test mode selection (L: normal, H: test mode)
TEST
3
I
LVTTL
–
Test setting (L: normal, H: test mode)
FCKM
77
I
LVTTL
–
FCLK8 test mode selection
(L: normal, H: test mode)
BCKM
111
I
LVTTL
–
Test mode selection of BCLK8 terminal.
(L: normal, H: test mode)
ATS1
139
I
Analog
–
Analog test input
Connect to GND normally.
ATS2
140
I
Analog
–
Analog test input
Connect to GND normally.
ATS3
142
I
Analog
–
Analog test input
Connect to GND normally.
VLPF1
149
O
Analog
–
Analog test output
Connect to GND via a 0.1
µ
F capacitor.
VLPF2
171
O
Analog
–
Analog test output
Connect to GND via a 0.1
µ
F capacitor.
Caution: Connect these terminals for test to GND unless otherwise instructed.
Summary of Contents for PDP-507XA
Page 41: ...PDP 507XD 41 5 6 7 8 5 6 7 8 C D F A B E ...
Page 44: ...PDP 507XD 44 1 2 3 4 1 2 3 4 C D F A B E 4 2 OVERALL CONNECTION DIAGRAM 2 2 ...
Page 45: ...PDP 507XD 45 5 6 7 8 5 6 7 8 C D F A B E ...
Page 55: ...PDP 507XD 55 5 6 7 8 5 6 7 8 C D F A B E ...
Page 78: ...PDP 507XD 78 1 2 3 4 1 2 3 4 C D F A B E 500ns div 500ns div 200ns div ...
Page 191: ...PDP 507XD 191 5 6 7 8 5 6 7 8 C D F A B E Block Diagram R2S11002AFT MAIN ASSY IC4701 AV SW ...