XV-DV830
129
5
7
8
5
7
8
C
D
F
A
B
E
SAA7893HL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
H_A[1]
H_DQ[15]
H_DQ[14]
GND_IO1
H_DQ[13]
H_DQ[12]
H_DQ[11]
H_DQ[10]
H_DQ[9]
VCC_IO1
H_DQ[8]
H_DQ[7]
H_DQ[6]
H_DQ[5]
H_DQ[4]
H_DQ[3]
GND_IO2
H_procclock
VCC_Core1
GND_Core1
sys_clk
H_DQ[2]
H_DQ[1]
H_CSn
H_DQ[0]
H_RWn
H_WAIT
H_IRQn
aud_clk
PCM_dclk_in
PCM_wclk_in
D_DQ[13]
D_DQ[2]
D_DQ[12]
GND_IO5
D_DQ[3]
D_DQ[11]
D_DQ[4]
D_DQ[10]
D_DQ[9]
D_DQ[6]
VCC_IO4
D_DQ[8]
D_DQ[7]
D_LDQM
D_UDQM
D_DQ[5]
D_clk
VCC_Core2
GND_Core2
GND_IO4
D_CASn
D_RASn
D_Wen
D_ADDR[11]
D_ADDR[12]
D_ADDR[9]
VCC_IO3
D_ADDR[13]
D_ADDR[8]
D_ADDR[10]
D_ADDR[7]
D_ADDR[0]
D_ADDR[6]
GND_IO3
D_ADDR[1]
D_ADDR[5]
D_ADDR[2]
D_ADDR[4]
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
90
89
88
87
86
85
84
83
82
81
100
101
102
99
98
97
96
95
94
93
92
91
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
120
119
118
117
116
115
114
113
112
111
128
127
126
125
124
123
122
121
110
109
108
107
106
105
104
103
DSD_PCM_9
DSD_PCM_10
VCC_IO6
DSD_PCM_8
DSD_PCM_7
DSD_PCM_6
DSD_PCM_5
DSD_PCM_4
GND_IO6
DSD_PCM_3
H_A[2]
H_A[3]
H_A[4]
H_A[5]
H_A[6]
H_A_sel
RESETn
DSD_PCM_11
DSD_PCM_2
DSD_PCM_1
DSD_PCM_0
D_DQ[15]
VCC_IO5
D_DQ[0]
D_DQ[14]
D_DQ[1]
UDE_req
Data_req
Be_dat(1)
Be_dat(2)
Be_dat(3)
Be_dat(4)
Be_dat(5)
Be_dat(6)
Be_dat(7)
TRST
PCM_CeLf_in
PCM_LeRi_in
PCM_LsRs_in
B_FLAG/SERR
B_SYNC/Sync
B_WCLK/SENB
B_DATA/Be_dat(0)
B_BCLK/SDCLK
TMS
VCC_IO2
TDO
TDI
TCK
H_sel[0]
H_sel[1]
D_ADDR[3]
¶
Pin Layout
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9
9
2
8
9
4
2
9
8
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9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
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