EL480.240-PR2/PR3 Users Manual
8
Interface Information
Planar EL Small Graphics Displays (SGD) incorporate an interface that is similar
to many LCD interfaces. This interface is supported by a variety of off-the shelf
chip sets which take care of all display control functionality, freeing the system
processor for other tasks. Designers select the chip set that best suits their
particular architecture and price point. This 4-bit LCD-type video interface
provides a low cost, flexible method for controlling display brightness and
power consumption.
Video Input Signals
The end of the top line of a frame is marked by VS, vertical sync signal as
shown in Figure 2. The end of each row of data is marked by HS.
The VS signal may be independently set to a CMOS low level at any time for
longer than one frame period. During the time of VS inactivity the display is
blank. Halting VS results in a standby condition to minimize power usage.
Figure 2. Video Input Timing Diagram.
Timing is compatible with LCD graphics controllers such as the SMOS display
controller.
