3.2.5
PCI Express lane 12 to lane 15
PCI Express lanes 12-15 of PEX 8619 are directly routed to PCI Express SLOT 12 to SLOT 15 with x1 link each
to form ports 3, 11, 13 and 15, as shown in
, and a Configuration Module is not required.
Lane 15
Lane 13
Lane 14
PEX 8619BA Base Board RDK Hardware Reference Manual – Version 1.0
Copyright © 2008 by PLX Technology, Inc. All rights reserved
8
Lane 12
x1
6 PCI Express Conn
ecto
rs
SLT15 SLT14 SLT13
Port 15
Port 13
Port 11
SLT12
A1
Lane 3-0
PEX 8619
(U100)
Port 3
Lane 4-7
L
ane 12-
15
Lane 8-11
Figure 7. Lanes 12 – 15 Hardware Connections on the RDK
3.3
Reference Clock Circuits
The RDK reference clock circuits contain one crystal-to HCSL clock generator ( U108) from On Semiconductor
(NB3N5573), two one-to-four differential clock fan out buffer (U28 and U61) from SpectraLinear (CY28400-2), two
1-to-10 differential clock drivers (U113-U114) from On Semiconductor (MC100LVEP111), AC coupling capacitors,
and resistors for source terminations and voltage dividers.
The clock circuits are designed to perform two major
clock functions: reference clock fan out and Spread-Spectrum Clock Isolation.
clock (CREFCLKp and CREFCLKn) from x4 PCI Express External Cable Connector J5 feeds into 1-to-4 fan out
buffer U28.
The outputs from U28 support the primary REFCLK of the PEX 8619 and connect to the inputs of
clock drivers U113 and U114.
The Constant frequency output from the clock generator (U108) is connected to a
1-to-4 fan out buffer U61. The outputs from U61 support the input to CFC_REFCK on the PEX 8619 as well as
inputs to U113 and U114. When Spread Spectrum Clocking Crossing is enabled, the PEX 8619 can be made part
of two clock domains. Port 0 is part of the SSC domain while all on-board PCI Express SLOT 1 to SLOT 15 are
part of the constant frequency domain. Add-in cards connected to SLOT1 – SLOT15 will operate in a constant
frequency clock. The SSC isolation feature can be enabled with a pull-down resistor on
STRAP_SSC_ISO_ENABLE# pin. On the RDK, this can be done in Dipswitch SW6 position 1 set to ‘ON’. This
feature is disabled on the RDK by default.
