PORTWELL NANO-6063 User's Guide
Copyright © Portwell 2022 NANO-6063 User's Guide
41
Feature
Description
Options
COMe PCIe Port
Control the PCI Express Root Port.
★
Enabled , Disabled
Connection Type
Built-In: a built-in device is connected to this root port.
Slot Implemented bit will be clear.
Slot: this root port connects to user-accessible slot.
Slot Implemented bit will be set.
★
Slot, Built-in
ASPM
Set the ASPM Level:
Force L0s – Force all links to L0s State
AUTO - BIOS auto configure
DISABLE – Disables ASPM
★
Disabled, L0s, L1, L0sL1, Auto
L1 Substates
PCI Express L1 Substates settings.
★
L1.1 & L1.2, L1.1, Disabled
ACS
Enable/Disable Access Control Services Extended Capability
★
Enabled , Disabled
PTM
Enable/Disable Precision Time Measurement
★
Disabled, Enabled
DPC
Enable/Disable Downstream Port Containment
★
Enabled , Disabled
EDPC
Enable/Disable Rootport extensions for Downstream Port Containment
★
Enabled , Disabled
URR
PCI Express Unsupported Request Reporting Enable/Disable.
★
Disabled, Enabled
FER
PCI Express Device Fatal Error Reporting Enable/Disable
★
Disabled, Enabled
NFER
PCI Express Device Non-Fatal Error Reporting Enable/Disable
★
Disabled, Enabled
CER
PCI Express Device Correctable Error Reporting Enable/Disable.
★
Disabled, Enabled
SEFE
Root PCI Express System Error on Fatal Error Enable/Disable.
★
Disabled, Enabled
SENFE
Root PCI Express System Error on Non-Fatal Error Enable/Disable.
★
Disabled, Enabled
SECE
Root PCI Express System Error on Correctable Error Enable/Disable.
★
Disabled, Enabled
PME SCI
PCI Express PME SCI Enable/Disable.
★
Enabled , Disabled
Summary of Contents for NANO-6063
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Page 61: ...PORTWELL NANO 6063 User s Guide Copyright Portwell 2022 NANO 6063 User s Guide 61 ...
Page 62: ...PORTWELL NANO 6063 User s Guide Copyright Portwell 2022 NANO 6063 User s Guide 62 Security ...
Page 80: ...PORTWELL NANO 6063 User s Guide Copyright Portwell 2022 NANO 6063 User s Guide 80 Serial ATA ...