10
Prestigio Cavaliere 141
Technical Service Manual
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Dynamic Clock Enable (CKE) control placing the SDRAM into Suspend to DRAM state
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High performance unified memory controller optimizing the DRAM bus utilization
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Programmable frame buffer size from 8MB and up to 64MB
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128KB SMRAM space re-mapping to A0000h, B0000h, or E0000h
Integrated A.G.P. Compliant Target/66Mhz Host-to-PCI Bridge
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AGP v2.0 Compliant
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Supports Graphic Window Size from 4MBytes to 256MBytes
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Supports Pipelined Process in CPU-to- A.G.P. Access
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Supports 8 Way, 16 Entries Page Table Cache for GART to Enhance A.G.P. Controller
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Read/Write Performance
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Supports PCI-to-PCI Bridge Function for Memory Write from 33Mhz PCI Bus to A.G.P. device
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Supports Additional AGP4X/2X interface and Fast Write Transaction
High Throughput SiS MuTIOL connect to SiS961 MuTIOL Media I/O
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Bi-directional 16 bit data bus
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Perform 533MB/s bandwidth in 66MHz x 4 mode
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Distributed arbitration strategy with enhanced mode of contiguous DMA data streaming
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Packet based, pipelining, and split transaction scheme
