power. The on-die 32-kB Level 1 instruction and data caches and the 1-MB Level 2 cache
with Advanced Transfer Cache Architecture enable significant performance improvement
over existing mobile processors. The processor also features a very advanced branch
prediction architecture that significantly reduces the number of mispredicted branches. The
processor
’
s Data Prefetch Logic speculatively fetches data to the L2 cache before an L1
cache requests occurs, resulting in reduced bus cycle penalties and improved performance.
The Streaming SIMD Extensions 2 (SSE2) enable break-through levels of performance in
multimedia applications including 3-D graphics, video decoding/encoding, and speech
recognition.The new packed double-precision floating-point instructions enhance
performance for applications that require greater range and precision, including scientific
and engineering applications and advanced 3-D geometry techniques, such as ray tracing.
The Intel Pentium M processor
’
s 400-MHz processor system bus utilizes a split-transaction,
deferred reply protocol. The 400-MHz processor system bus uses Source-Synchronous
Transfer (SST) of address and data to improve performance by transferring data four times
per bus clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the
address bus can deliver addresses two times per bus clock and is referred to as a
“
double-
clocked
”
or 2X address bus.Working together, the 4X data bus and 2X address bus provide
a data bus bandwidth of up to 3.2 Gbytes/second. The processor system bus uses Advanced
Gunning Transceiver Logic (AGTL+)signal technology, a variant of GTL+ signalling
technology with low power enhancements.
The processor features Enhanced Intel SpeedStep technology, which enables real-time
dynamic switching between multiple voltage and frequency points instead of two points
supported on previous versions of Intel SpeedStep technology. This results in optimal
performance without compromising low power. The processor features the Auto Halt,
Stop-Grant, Deep Sleep, and Deeper Sleep low power states.
The Intel Pentium M processor utilizes socketable Micro Flip-Chip Pin Grid Array (Micro-
FCPGA) and surface mount Micro Flip-Chip Ball Grid Array (Micro-FCBGA) package
technology. The Micro-FCPGA package plugs into a 479-hole, surface-mount, Zero
Insertion Force (ZIF) socket, which is referred to as the mPGA479M socket.
This document includes specifications for the Intel Pentium M processor at Highest
Frequency Mode (HFM) core frequencies of 1.30, 1.40, 1.50, and 1.60 GHz, the Low
Voltage Intel Pentium M processor at HFM core frequency of 1.10 GHz and the Ultra Low
Voltage Intel Pentium M processor at HFM core frequency of 900 MHz.
4.5 System Core Logic
4.5.1 Intel 852GM Chipset GMCH Features
Processor/Host Bus Support
―
Mobile Intel
®
Pentium
®
4 Processor-M (478-pin package)
. Supports the Intel Pentium 4 Processor-M subset of the Enhanced Mode Scalable Bus
Protocol
. 2X Address, 4X data
. Intel Pentium 4 Processor-M System Bus interrupt delivery
. Supports system bus at 400-MHz or 3.2 GB/s
. Supports host Dynamic Bus Inversion (DBI)
. Supports 32-bit host bus addressing
TECHNICAL SERVICE MANUAL
Prestigio Cavaliere 142
71
