•
Enhanced DMA Controller, Interrupt Controller, and Timer Functions
•
Integrated IDE controller supports Ultra ATA100/66/33
•
USB host interface with support for 6 USB ports; 3 UHCI host controllers; 1 EHCI
high-speed USB 2.0 Host Controller
•
Integrated LAN Controller
•
System Management Bus (SMBus) Specification, Version 2.0 with additional support
for I2C devices
•
Supports Audio Codec
’
97, Revision 2.3 specification (a.k.a., AC
’
97 Component
Specification, Revision 2.3). Link for Audio and Telephony codecs (up to 7 channels)
•
Low Pin Count (LPC) interface
•
Firmware Hub (FWH) interface support
•
Alert On LAN* (AOL) and Alert On LAN 2* (AOL2)
Hub Architecture
As I/O speeds increase, the demand placed on the PCI bus by the I/O bridge has become
significant. With AC
’
97, USB 2.0, and Ultra ATA/100, coupled with the existing USB, I/O
requirements could impact PCI bus performance. The chipset
’
s
hub interface architecture
ensures that the I/O subsystem; both PCI and the integrated I/O features (IDE, AC
‘
97,
USB, etc.), receive adequate bandwidth. By placing the I/O bridge on the hub interface
(instead of PCI), the hub architecture ensures that both the I/O functions integrated into the
ICH4 and the PCI peripherals obtain the bandwidth necessary for peak performance.
PCI Interface
The ICH4 PCI interface provides a 33-MHz, Rev. 2.2 compliant implementation. All PCI
signals are 5-V tolerant, except PME#. The ICH4 integrates a PCI arbiter that supports up
to six external PCI bus masters in addition to the internal ICH4 requests.
IDE Interface (Bus Master Capability and Synchronous DMA Mode)
The fast IDE interface supports up to four IDE devices providing an interface for IDE hard
disks and ATAPI devices. Each IDE device can have independent timings. The IDE
interface supports PIO IDE transfers up to 16 Mbytes/sec and Ultra ATA transfers up 100
Mbytes/sec. It does not consume any ISA DMA resources. The IDE interface integrates
16x32-bit buffers for optimal transfers.
The ICH4
’
s IDE system contains two independent IDE signal channels. They can be
electrically isolated independently. They can be configured to the standard primary and
secondary channels (four devices). There are integrated series resistors on the data and
control lines (see Section 5.15,
“
IDE Controller (D31:F1)
”
on page 5-175
for details).
Low Pin Count (LPC) Interface
The ICH4 implements an LPC Interface as described in the LPC 1.0 specification. The
TECHNICAL SERVICE MANUAL
Prestigio Cavaliere 142
73
