Low Pin Count (LPC) Bridge function of the ICH4 resides in PCI Device 31:Function 0. In
addition to the LPC bridge interface function, D31:F0 contains other functional units
including DMA, Interrupt Controllers, Timers, Power Management, System Management,
GPIO, and RTC.
Note that in the current chipset platform, the Super I/O (SIO) component has migrated to
the Low Pin Count (LPC) interface. Migration to the LPC interface allows for lower cost
Super I/O designs.
Compatibility Modules (DMA Controller, Timer/Counters, Interrupt Controller)
The DMA controller incorporates the logic of two 82C37 DMA controllers, with seven
independently programmable channels. Channels 0
–
3 are hardwired to 8-bit, count-by-byte
transfers, and channels 5
–
7 are hardwired to 16-bit, count-by-word transfers. Any two of
the seven DMA channels can be programmed to support fast Type-F transfers.
The ICH4 supports two types of DMA (LPC and PC/PCI). DMA via LPC is similar to ISA
DMA. LPC DMA and PC/PCI DMA use the ICH4
’
s DMA controller. The PC/PCI
protocol allows PCI-based peripherals to initiate DMA cycles by encoding requests and
grants via two PC/PCI REQ#/GNT# pairs.
LPC DMA is handled through the use of the LDRQ# lines from peripherals and special
encodings on LAD[3:0] from the host. Single, Demand, Verify, and Increment modes are
supported on the LPC interface. Channels 0
–
3 are 8 bit channels. Channels 5
–
7 are 16 bit
channels. Channel 4 is reserved as a generic bus master request.
The timer/counter block contains three counters that are equivalent in function to those
found in one 82C54 programmable interval timer. These three counters are combined to
provide the system timer function, and speaker tone. The 14.31818-MHz oscillator input
provides the clock source for these three counters.
The ICH4 provides an ISA-Compatible Programmable Interrupt Controller (PIC) that
incorporates the functionality of two 82C59 interrupt controllers. The two interrupt
controllers are cascaded so that 14 external and two internal interrupts are possible. In
addition, the ICH4 supports a serial interrupt scheme.
All of the registers in these modules can be read and restored. This is required to save and
restore system state after power has been removed and restored to the platform.
Advanced Programmable Interrupt Controller (APIC)
In addition to the standard ISA compatible Programmable Interrupt Controller (PIC)
described in the previous section, the ICH4 incorporates the Advanced Programmable
Interrupt Controller
Universal Serial Bus (USB) Controller
The ICH4 contains an Enhanced Host Controller Interface (EHCI) compliant host ontroller
that supports USB high-speed signaling. High-speed USB 2.0 allows data transfers up to
480 Mb/s which is 40 times faster than full-speed USB. The ICH4 also contains three
Universal Host Controller Interface (UHCI) controllers that support USB full-speed and
TECHNICAL SERVICE MANUAL
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