As required by the 1394 Open Host Controller Interface Specification (OHCI) and IEEE Std
1394a-2000, internal control registers are memory-mapped and nonprefetchable. The PCI
configuration header is accessed through configuration cycles specified by PCI, and it provides
plug-and-play (PnP) compatibility. Furthermore, the TSB43AB22A device is compliant with the
PCI Bus Power Management Interface Specification as specified by the PC 2001 Design Guide
requirements. The TSB43AB22A device supports the D0, D1, D2, and D3 power states.
The TSB43AB22A design provides PCI bus master bursting, and it is capable of transferring a
cacheline of data at 132M bytes/s after connection to the memory controller. Because PCI latency
can be large, deep FIFOs are provided to buffer the 1394 data. The TSB43AB22A device provides
physical write posting buffers and a highly-tuned physical data path for SBP-2 performance. The
TSB43AB22A device also provides multiple isochronous contexts, multiple cacheline burst
transfers, advanced internal arbitration, and bus-holding buffers.
An advanced CMOS process achieves low power consumption and allows the TSB43AB22A
device to operate at PCI clock rates up to 33 MHz.
The TSB43AB22A PHY-layer provides the digital and analog transceiver functions needed to
implement a two-port node in a cable-based 1394 network. Each cable port incorporates two
differential line transceivers. The transceivers include circuitry to monitor the line conditions as
needed for determining connection status, for initialization and arbitration, and for packet reception
and transmission.
The TSB43AB22A PHY-layer requires only an external 24.576-MHz crystal as a reference for
the cable ports. An external clock may be provided instead of a crystal. An internal oscillator drives
an internal phase-locked loop (PLL), which generates the required 393.216-MHz reference signal.
This reference signal is internally divided to provide the clock signals that control transmission of
the outbound encoded strobe and data information. A 49.152-MHz clock signal is supplied to the
integrated LLC for synchronization and is used for resynchronization of the received data.
Data bits to be transmitted through the cable ports are received from the integrated LLC and are
latched internally in synchronization with the 49.152-MHz system clock. These bits are combined
serially, encoded, and transmitted at 98.304M, 196.608M, or 393.216M bits/s (referred to as S100,
S200, or S400 speeds, respectively) as the outbound data-strobe information stream. During
transmission, the encoded data information is transmitted differentially on the twisted-pair B (TPB)
cable pair(s), and the encoded strobe information is transmitted differentially on the twisted-pair A
(TPA) cable pair(s).
TECHNICAL SERVICE MANUAL
Prestigio Nobile 159W
1-23
Summary of Contents for NOBILE 159W
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