suspended). In this low-power mode, the TSB43AB22A device disables its internal clock generators
and also disables various voltage and current reference circuits, depending on the state of the ports
(some reference circuitry must remain active in order to detect new cable connections,
disconnections, or incoming TPBIAS, for example). The lowest power consumption (the
ultralow-power sleep mode) is attained when all ports are either disconnected or disabled with the
port interrupt enable bit cleared.
The TSB43AB22A device exits the low-power mode when bit 19 (LPS) in the host controller
control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register) is set to
1 or when a port event occurs which requires that the TSB43AB22A device to become active in
order to respond to the event or to notify the LLC of the event (for example, incoming bias is
detected on a suspended port, a disconnection is detected on a suspended port, or a new connection is
detected on a nondisabled port). When the TSB43AB22A device is in the low-power mode, the
internal 49.153-MHz clock becomes active (and the integrated PHY layer becomes operative) within
2 ms after bit 19 (LPS) in the host controller control register at OHCI offset 50h/54h (see Section
4.16, Host Controller Control Register) is set to 1.
The TSB43AB22A device supports hardware enhancements to better support digital video (DV)
and MPEG data stream reception and transmission. These enhancements are enabled through the
isochronous receive digital video
enhancements register at OHCI offset A88h (see Chapter 5, TI Extension Registers). The
enhancements include automatic timestamp insertion for transmitted DV and MPEG-formatted
streams and common isochronous packet (CIP) header stripping for received DV streams.
The CIP format is defined by the IEC 61883-1:1998 specification. The enhancements to the
isochronous data contexts are implemented as hardware support for the synchronization timestamp
for both DV and MPEG CIP formats. The TSB43AB22A device supports modification of the
synchronization timestamp field to ensure that the value inserted via software is not stale
—
that is,
the value is less than the current cycle timer when the packet is transmitted.
1.1.1.Features
Fully compliant with provisions of IEEE Std 1394-1995 for a high-performance serial bus
†
and
IEEE Std 1394a-2000
Fully interoperable with FireWire and i.LINK implementations of IEEE Std 1394
Compliant with Intel Mobile Power Guideline 2000
Full IEEE Std 1394a-2000 support includes: connection debounce, arbitrated short reset,
multispeed concatenation, arbitration acceleration, fly-by concatenation, and port
disable/suspend/resume
Power-down features to conserve energy in battery-powered applications include: automatic device
TECHNICAL SERVICE MANUAL
Prestigio Nobile 159W
1-25
Summary of Contents for NOBILE 159W
Page 1: ...PRESTIGIO NOBILE 159W TECHNICAL SERVICE MANUAL ...
Page 2: ......
Page 38: ......
Page 76: ......
Page 81: ...3 6 LCD Module Assembly TECHNICALSERVICEMANUAL PrestigioNobile159W 3 6 ...
Page 83: ......
Page 92: ...25 System Disassembly TECHNICALSERVICEMANUAL PrestigioNobile159W 4 10 ...
Page 96: ......
Page 102: ...4 Fasten 1 screw of the HDD cover TECHNICALSERVICEMANUAL PrestigioNobile159W 5 7 ...
Page 105: ......
Page 127: ...www prestigio com ...
