power down during suspend, PCI power management for link-layer, and inactive ports powered
down
Ultralow-power sleep mode
Two IEEE Std 1394a-2000 fully compliant cable ports at 100M bits/s, 200M bits/s, and 400M bits/s
Cable ports monitor line conditions for active connection to remote node
Cable power presence monitoring
Separate cable bias (TPBIAS) for each port
1.8-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling
environments
Physical write posting of up to three outstanding transactions
PCI burst transfers and deep FIFOs to tolerate large host latency
PCI_CLKRUN# protocol
External cycle timer control for customized synchronization
Extended resume signaling for compatibility with legacy DV components
PHY-Link logic performs system initialization and arbitration functions
PHY-Link encode and decode functions included for data-strobe bit level encoding
PHY-Link incoming data resynchronized to local clock
Low-cost 24.576-MHz crystal provides transmit and receive data at 100M bits/s, 200M bits/s, and
400M bits/s
Node power class information signaling for system power management
Serial ROM interface supports 2-wire serial EEPROM devices
Two general-purpose I/Os
Register bits give software control of contender bit, power class bits, link active control bit, and
IEEE Std 1394a-2000 features
Fabricated in advanced low-power CMOS process
PCI and CardBus register support
Isochronous receive dual-buffer mode
Out-of-order pipelining for asynchronous transmit requests
Register access fail interrupt when the PHY SCLK is not active
H. LAN
–
Ethernet Controller
–
RTL8100C
TECHNICAL SERVICE MANUAL
Prestigio Nobile 159W
1-26
Summary of Contents for NOBILE 159W
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Page 102: ...4 Fasten 1 screw of the HDD cover TECHNICALSERVICEMANUAL PrestigioNobile159W 5 7 ...
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