System Interrupts
Supports 8259 and processor system bus interrupt delivery mechanism
Supports interrupts signaled as upstream Memory Writes from AGP/PCI (PCI semantics only)
and hub interface
MSI sent to the CPU through the System Bus
From IOxAPIC in ICH4-M
Supports peer MSI between hub interface and AGP
Provides redirection for upstream interrupts to the System Bus
Accelerated Graphics Port (AGP) Interface
Supports a single AGP device (either through a connector or on the motherboard)
AGP Support
Supports AGP 2.0 including 1x, 2x, and 4x AGP data transfers and 2x/4x Fast Write protocol
Supports only 1.5-V AGP electricals
32 deep AGP request queue
PCI semantic (FRAME# initiated) accesses to DRAM are snooped
AGP semantic (PIPE# and SBA) accesses to DRAM are not snooped
High priority access support
Hierarchical PCI configuration mechanism
Delayed transaction support for AGP-to- DRAM FRAME# semantic reads that can not be
serviced immediately
32-bit upstream address support for inbound AGP and PCI cycles
32-bit downstream address support for outbound PCI and Fast Write cycles
AGP Busy/Stop Protocol
AGP Clamping and Sense Amp Control
Hub Interface to ICH4-M
266 MB/s point-to-point hub interface to ICH4-M
66-MHz base clock
Supports the following traffic types to the ICH4-M
1
Hub interface-to-AGP memory writes
2
Hub interface-to-DRAM
3
CPU-to-hub interface
4
Messaging
-MSI Interrupt messages
-Power Management state change
-SMI, SCI, and SERR error indication
TECHNICAL SERVICE MANUAL
Prestigio Nobile 159W
1-6
Summary of Contents for NOBILE 159W
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