V6402, V6404, V6406, V6408
and V6418 HD converters
HU-V6402&4&6&8&18
7
1.2
Block Diagram
Ext. Flash
LVDS Video In (3 pairs Data + 1 pair Clock)
Tri-Le vel Sync or
Black & Burst
HD SDI Input2
3.3V, 1.8V, 1.5V
Ref F
De-Serializer
I/O Daughter Card
SD SDI Output2
I/O Daughter Card
2M x 32
Clock-Generator
Genlock
2D Scaler
Cable EQ
Cable Driver
V
to
/f
ro
m
V
6302
LVDS Misc I/O (Clk, F, RxD, TxD, etc.)
Ref V
Ref H
DLY Pulse Output
Ref Data EEProm
System Control Interface (DART)
&
SDRAM
&
F
20-Bit YUV
Multi-Rate
V6402 / V6404 / V6408 / V6418
H
Reclocker
Sync Separator
I2C Interface
Reference Input
Power Supplies
D
A
RT
Cable Driver
PLL
SD SDI Output1
Cable EQ
HD SDI Input1
Reclocked HD Output
2M x 32
SDRAM
SDRAM
2M x 32
SDRAM
2M x 32
Audio De-Embedding
Frame-Sync
Loop Through Ref.
Serializer
VCO
VCO
TPG
20
-B
it
20
-B
it
20
-B
it
20
-B
it
Ref CLK27
Internal I2C
LVDS Video Out (3 pairs Data + 1 pair Clock)
JTAG
v
ia
Rea
r
P
a
n
el
Serial Control Bus
'41 Style Front Panel
Control & Status Indication
FPGA
H8S/2633
Hitachi
I nput CLK
F
R
e
f
C
L
KB
Ref CLK74
Scaler Output CLK
Output CLK
Ref CLK74
Ref CLK A
IN_CLK
PRC_C LK
CLKO UT
R
xD
20-Bit YUV
20-Bit YUV
30-Bit RGB or 10-Bit YUV (muxed)
21-Bit LVDS Rx
21-Bit LVDS Tx
21
-B
it
OUT_C LK
21
-B
it
Ref CLK B
Ref CLK74
SDRAM
64
-B
it
Down- & Cross-
Converter Option
2M x 32
Serial Control
Serial Control
CPLD
14.7456MHz
27MHz
Ref CLK27
Ref CLK74
(not fitted on V6402)
(A
udio
Pr
o
c
e
s
so
r)
Ref CLK27
Ref CLK74
Ref CLK74
Ref CLK27
Ref CLK A
Ref CLK B
Clock Distribution
Ref CLK A
Ref CLK A
Ref CLK B
Ref CLK B
Ref CLK A
Ref CLK B
T
xD
bet ween H8's on V640x and V6302
Asynchronous Serial Comms Port
27/74MHz Clock
74/27MHz Clock
Frame Store Options:
(84-Bit wide optional)
96MByte Max (3x 8Mx32)
16MByte Min (2x 2Mx32)
'Beagle'
Audio Re-Embedding
